Peter Crosthwaite f7838b5290 arm: cortex-a9: Fix cache-line size and associativity ... For A9, The cache associativity is 4 and the lines size is 32B. Self identify in CCSIDR accordingly. Cache size remains at 16k. QEMU doesn't emulate caches, but we should still report the correct cache-line size to the guest. Some guests (like u-boot) complain if the cache-line size mismatches a requested flush or invalidate operation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1de6bd40155a1d2f2e93e24b1b1d1d677a432641.1408346233.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2014-08-19 19:02:40 +01:00
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arm_ldst.h
arm-semi.c
cpu64.c
cpu-qom.h
cpu.c	arm: cortex-a9: Fix cache-line size and associativity	2014-08-19 19:02:40 +01:00
cpu.h
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c
helper-a64.h
helper.c
helper.h
internals.h
iwmmxt_helper.c
kvm32.c
kvm64.c
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c
machine.c
Makefile.objs
neon_helper.c
op_addsub.h
op_helper.c
translate-a64.c
translate.c
translate.h