Yongbok Kim 6b9c26fb5e disas/mips: fix disassembling R6 instructions
In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF
and CACHE instructions have 9 bits offsets.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-07-15 14:07:20 +01:00
..
2015-07-09 15:20:41 +02:00
2013-03-18 19:40:34 +01:00
2013-03-23 14:25:41 +00:00
2015-02-03 12:27:05 -08:00