fcf5ef2ab5
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
322 lines
8.2 KiB
C
322 lines
8.2 KiB
C
/*
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* PowerPC gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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static int ppc_gdb_register_len_apple(int n)
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{
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switch (n) {
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case 0 ... 31:
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/* gprs */
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return 8;
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case 32 ... 63:
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/* fprs */
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return 8;
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case 64 ... 95:
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return 16;
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case 64+32: /* nip */
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case 65+32: /* msr */
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case 67+32: /* lr */
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case 68+32: /* ctr */
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case 69+32: /* xer */
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case 70+32: /* fpscr */
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return 8;
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case 66+32: /* cr */
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return 4;
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default:
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return 0;
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}
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}
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static int ppc_gdb_register_len(int n)
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{
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switch (n) {
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case 0 ... 31:
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/* gprs */
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return sizeof(target_ulong);
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case 32 ... 63:
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/* fprs */
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if (gdb_has_xml) {
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return 0;
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}
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return 8;
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case 66:
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/* cr */
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return 4;
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case 64:
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/* nip */
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case 65:
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/* msr */
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case 67:
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/* lr */
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case 68:
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/* ctr */
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case 69:
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/* xer */
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return sizeof(target_ulong);
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case 70:
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/* fpscr */
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if (gdb_has_xml) {
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return 0;
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}
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return sizeof(target_ulong);
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default:
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return 0;
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}
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}
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/* We need to present the registers to gdb in the "current" memory ordering.
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For user-only mode we get this for free; TARGET_WORDS_BIGENDIAN is set to
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the proper ordering for the binary, and cannot be changed.
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For system mode, TARGET_WORDS_BIGENDIAN is always set, and we must check
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the current mode of the chip to see if we're running in little-endian. */
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void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
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{
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#ifndef CONFIG_USER_ONLY
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if (!msr_le) {
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/* do nothing */
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} else if (len == 4) {
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bswap32s((uint32_t *)mem_buf);
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} else if (len == 8) {
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bswap64s((uint64_t *)mem_buf);
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} else {
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g_assert_not_reached();
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}
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#endif
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}
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/* Old gdb always expects FP registers. Newer (xml-aware) gdb only
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* expects whatever the target description contains. Due to a
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* historical mishap the FP registers appear in between core integer
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* regs and PC, MSR, CR, and so forth. We hack round this by giving the
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* FP regs zero size when talking to a newer gdb.
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*/
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int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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int r = ppc_gdb_register_len(n);
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if (!r) {
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return r;
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}
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if (n < 32) {
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/* gprs */
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gdb_get_regl(mem_buf, env->gpr[n]);
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} else if (n < 64) {
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/* fprs */
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stfq_p(mem_buf, env->fpr[n-32]);
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} else {
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switch (n) {
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case 64:
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gdb_get_regl(mem_buf, env->nip);
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break;
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case 65:
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gdb_get_regl(mem_buf, env->msr);
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break;
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case 66:
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{
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uint32_t cr = 0;
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int i;
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for (i = 0; i < 8; i++) {
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cr |= env->crf[i] << (32 - ((i + 1) * 4));
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}
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gdb_get_reg32(mem_buf, cr);
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break;
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}
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case 67:
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gdb_get_regl(mem_buf, env->lr);
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break;
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case 68:
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gdb_get_regl(mem_buf, env->ctr);
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break;
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case 69:
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gdb_get_regl(mem_buf, env->xer);
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break;
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case 70:
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gdb_get_reg32(mem_buf, env->fpscr);
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break;
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}
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}
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ppc_maybe_bswap_register(env, mem_buf, r);
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return r;
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}
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int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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int r = ppc_gdb_register_len_apple(n);
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if (!r) {
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return r;
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}
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if (n < 32) {
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/* gprs */
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gdb_get_reg64(mem_buf, env->gpr[n]);
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} else if (n < 64) {
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/* fprs */
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stfq_p(mem_buf, env->fpr[n-32]);
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} else if (n < 96) {
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/* Altivec */
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stq_p(mem_buf, n - 64);
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stq_p(mem_buf + 8, 0);
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} else {
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switch (n) {
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case 64 + 32:
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gdb_get_reg64(mem_buf, env->nip);
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break;
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case 65 + 32:
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gdb_get_reg64(mem_buf, env->msr);
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break;
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case 66 + 32:
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{
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uint32_t cr = 0;
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int i;
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for (i = 0; i < 8; i++) {
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cr |= env->crf[i] << (32 - ((i + 1) * 4));
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}
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gdb_get_reg32(mem_buf, cr);
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break;
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}
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case 67 + 32:
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gdb_get_reg64(mem_buf, env->lr);
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break;
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case 68 + 32:
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gdb_get_reg64(mem_buf, env->ctr);
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break;
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case 69 + 32:
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gdb_get_reg64(mem_buf, env->xer);
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break;
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case 70 + 32:
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gdb_get_reg64(mem_buf, env->fpscr);
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break;
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}
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}
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ppc_maybe_bswap_register(env, mem_buf, r);
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return r;
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}
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int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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int r = ppc_gdb_register_len(n);
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if (!r) {
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return r;
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}
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ppc_maybe_bswap_register(env, mem_buf, r);
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if (n < 32) {
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/* gprs */
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env->gpr[n] = ldtul_p(mem_buf);
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} else if (n < 64) {
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/* fprs */
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env->fpr[n-32] = ldfq_p(mem_buf);
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} else {
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switch (n) {
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case 64:
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env->nip = ldtul_p(mem_buf);
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break;
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case 65:
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ppc_store_msr(env, ldtul_p(mem_buf));
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break;
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case 66:
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{
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uint32_t cr = ldl_p(mem_buf);
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int i;
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for (i = 0; i < 8; i++) {
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env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
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}
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break;
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}
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case 67:
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env->lr = ldtul_p(mem_buf);
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break;
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case 68:
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env->ctr = ldtul_p(mem_buf);
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break;
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case 69:
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env->xer = ldtul_p(mem_buf);
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break;
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case 70:
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/* fpscr */
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store_fpscr(env, ldtul_p(mem_buf), 0xffffffff);
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break;
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}
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}
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return r;
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}
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int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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int r = ppc_gdb_register_len_apple(n);
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if (!r) {
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return r;
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}
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ppc_maybe_bswap_register(env, mem_buf, r);
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if (n < 32) {
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/* gprs */
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env->gpr[n] = ldq_p(mem_buf);
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} else if (n < 64) {
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/* fprs */
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env->fpr[n-32] = ldfq_p(mem_buf);
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} else {
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switch (n) {
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case 64 + 32:
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env->nip = ldq_p(mem_buf);
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break;
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case 65 + 32:
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ppc_store_msr(env, ldq_p(mem_buf));
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break;
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case 66 + 32:
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{
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uint32_t cr = ldl_p(mem_buf);
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int i;
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for (i = 0; i < 8; i++) {
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env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
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}
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break;
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}
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case 67 + 32:
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env->lr = ldq_p(mem_buf);
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break;
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case 68 + 32:
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env->ctr = ldq_p(mem_buf);
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break;
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case 69 + 32:
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env->xer = ldq_p(mem_buf);
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break;
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case 70 + 32:
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/* fpscr */
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store_fpscr(env, ldq_p(mem_buf), 0xffffffff);
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break;
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}
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}
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return r;
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}
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