Palmer Dabbelt fd990e86a7 RISC-V: Add a missing "," in riscv_excp_names ... This would almost certainly cause the exception names to be reported incorrectly. Coverity found the issue (CID 1420223). As per Peter's suggestion, I've also added a comma at the end of the list to avoid the issue reappearing in the future. Fixes: ab67a1d07a ("target/riscv: Add support for the new execption numbers") Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-03-05 12:01:43 -08:00
..
insn_trans	target/riscv: Remove the hret instruction	2020-02-27 13:45:45 -08:00
cpu_bits.h	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	2020-02-27 13:46:33 -08:00
cpu_helper.c	target/riscv: Emulate TIME CSRs for privileged mode	2020-02-27 13:46:36 -08:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
cpu-param.h
cpu.c	RISC-V: Add a missing "," in riscv_excp_names	2020-03-05 12:01:43 -08:00
cpu.h	target/riscv: Emulate TIME CSRs for privileged mode	2020-02-27 13:46:36 -08:00
csr.c	target/riscv: Emulate TIME CSRs for privileged mode	2020-02-27 13:46:36 -08:00
fpu_helper.c	target/riscv: rationalise softfloat includes	2019-08-19 12:07:13 +01:00
gdbstub.c	target/riscv: Add the Hypervisor CSRs to CPUState	2020-02-27 13:45:25 -08:00
helper.h
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode	target/riscv: Remove the hret instruction	2020-02-27 13:45:45 -08:00
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
Makefile.objs	riscv: hmp: Add a command to show virtual memory mappings	2019-09-17 08:42:43 -07:00
monitor.c	riscv: hmp: Add a command to show virtual memory mappings	2019-09-17 08:42:43 -07:00
op_helper.c	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	2020-02-27 13:46:33 -08:00
pmp.c	target/riscv: PMP violation due to wrong size parameter	2019-10-28 08:46:33 -07:00
pmp.h	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-06-23 23:44:41 -07:00
trace-events	target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events	2019-09-17 08:42:42 -07:00
translate.c	target/riscv: Add the MSTATUS_MPV_ISSET helper macro	2020-02-27 13:46:33 -08:00