6e8b990354
This is the combination of frozen bit and counter type, on a per
counter basis. So far this is only used by HFLAGS_INSN_CNT, but
will be used more later.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
[danielhb: fixed PMC4 cyc_cnt shift, insn run latch code,
MMCR0_FC handling, "PMC[1-6]" comment]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220103224746.167831-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
25 lines
558 B
C
25 lines
558 B
C
/*
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* PMU emulation helpers for TCG IBM POWER chips
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*
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* Copyright IBM Corp. 2021
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*
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* Authors:
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* Daniel Henrique Barboza <danielhb413@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef POWER8_PMU
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#define POWER8_PMU
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void cpu_ppc_pmu_init(CPUPPCState *env);
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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void pmu_update_summaries(CPUPPCState *env);
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#else
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static inline void pmu_update_summaries(CPUPPCState *env) { }
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#endif
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#endif
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