qemu-e2k/target/riscv
Peter Maydell 5005aed8a7 testing, doc and gdbstub updates:
- add sqlite3 to openSUSE image
   - mark CRIS as deprecated
   - re-enable the TCG plugin tests
   - use select for semihosting
   - implement syscall catching in gdbstub
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Merge tag 'pull-maintainer-updates-090224-1' of https://gitlab.com/stsquad/qemu into staging

testing, doc and gdbstub updates:

  - add sqlite3 to openSUSE image
  - mark CRIS as deprecated
  - re-enable the TCG plugin tests
  - use select for semihosting
  - implement syscall catching in gdbstub

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# gpg: Signature made Fri 09 Feb 2024 17:54:28 GMT
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* tag 'pull-maintainer-updates-090224-1' of https://gitlab.com/stsquad/qemu:
  tests/tcg: Add the syscall catchpoint gdbstub test
  gdbstub: Implement catching syscalls
  gdbstub: Add syscall entry/return hooks
  gdbstub: Allow specifying a reason in stop packets
  gdbstub: Expose TARGET_SIGTRAP in a target-agnostic way
  kconfig: use "select" to enable semihosting
  Revert "hw/elf_ops: Ignore loadable segments with zero size"
  configure: run plugin TCG tests again
  docs: mark CRIS support as deprecated
  tests/docker: Add sqlite3 module to openSUSE Leap container

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-12 14:14:10 +00:00
..
insn_trans target/riscv: Enable xtheadsync under user mode 2024-02-09 20:43:14 +10:00
kvm target/riscv: Move misa_mxl_max to class 2024-02-09 20:43:14 +10:00
tcg target/riscv: Validate misa_mxl_max only once 2024-02-09 20:43:14 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: FCSR doesn't contain vxrm and vxsat 2024-02-09 20:43:14 +10:00
cpu_cfg.h target/riscv: Add Zaamo and Zalrsc extension infrastructure 2024-02-09 20:43:14 +10:00
cpu_helper.c target/riscv: change vext_get_vlmax() arguments 2024-02-09 20:43:14 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h target/riscv: add rv32i, rv32e and rv64e CPUs 2024-02-09 20:49:41 +10:00
cpu.c target/riscv: add rv32i, rv32e and rv64e CPUs 2024-02-09 20:49:41 +10:00
cpu.h target/riscv: support new isa extension detection devicetree properties 2024-02-09 20:43:14 +10:00
crypto_helper.c
csr.c target/riscv: Use RISCVException as return type for all csr ops 2024-02-09 20:43:14 +10:00
debug.c target/riscv: Implement optional CSR mcontext of debug Sdtrig extension 2024-02-09 20:40:32 +10:00
debug.h
fpu_helper.c
gdbstub.c target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS 2024-02-09 20:43:14 +10:00
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h
Kconfig kconfig: use "select" to enable semihosting 2024-02-09 17:52:30 +00:00
m128_helper.c
machine.c target/riscv: Move misa_mxl_max to class 2024-02-09 20:43:14 +10:00
meson.build
monitor.c
op_helper.c
pmp.c
pmp.h
pmu.c
pmu.h
riscv-qmp-cmds.c
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c target/riscv: Move misa_mxl_max to class 2024-02-09 20:43:14 +10:00
vcrypto_helper.c
vector_helper.c target/riscv: change vext_get_vlmax() arguments 2024-02-09 20:43:14 +10:00
vector_internals.c
vector_internals.h
xthead.decode
XVentanaCondOps.decode
zce_helper.c