361 lines
10 KiB
C
361 lines
10 KiB
C
#include "qemu/osdep.h"
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#include "qemu.h"
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#include "disas/disas.h"
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#include "exec/translator.h"
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#include "tcg/tcg-op.h"
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typedef struct {
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DisasContextBase base;
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target_ulong pc;
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target_ulong npc;
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} DisasContext;
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static struct unpacked_instr {
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unsigned int hs;
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unsigned int ss;
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unsigned int als[6];
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unsigned int cs0;
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unsigned short ales[6];
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unsigned int cs1;
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unsigned short aas[6];
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unsigned short half_gap;
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/* It should be impossible to have more than 16 words of GAP
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in principle. */
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unsigned int gap[16];
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unsigned int lts[4];
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unsigned int pls[3];
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unsigned int cds[3];
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unsigned char ss_present;
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unsigned char als_present[6];
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unsigned char cs0_present;
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unsigned char ales_present[6];
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unsigned char cs1_present;
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unsigned char aas_present[6];
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unsigned char half_gap_present;
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unsigned char gap_present[16];
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unsigned char lts_present[4];
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unsigned char pls_present[3];
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unsigned char cds_present[3];
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unsigned int api_l[2];
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unsigned int api_r[2];
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} unpacked_instr;
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// TODO: return error on invalid instruction
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static target_ulong unpack_instr(CPUE2KState *env, DisasContext *ctx, target_ulong pos,
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struct unpacked_instr *instr)
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{
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unsigned int i;
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target_ulong gap, next_pc = pos + 8;
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int hsyll_cntr = 0;
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unsigned int hs;
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unsigned int mdl;
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memset (instr, 0, sizeof (unpacked_instr));
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hs = translator_ldl(env, &ctx->base, pos);
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pos += 4;
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instr->hs = hs;
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next_pc += ((hs & 0x70) >> 4) * 8;
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/* Check for SS. */
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if (hs & (0x1 << 12))
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{
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instr->ss_present = 1;
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instr->ss = translator_ldl(env, &ctx->base, pos);
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pos += 4;
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}
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/* Check for available ALS syllables. */
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for (i = 0; i < 6; i++)
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{
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if (hs & (1 << (26 + i)))
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{
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instr->als_present[i] = 1;
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instr->als[i] = translator_ldl(env, &ctx->base, pos);
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pos += 4;
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}
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}
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/* Check for CS0. */
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if (hs & (0x1 << 14))
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{
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instr->cs0_present = 1;
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instr->cs0 = translator_ldl(env, &ctx->base, pos);
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pos += 4;
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}
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/* If either `ALES5' or `ALES2' has been marked as present in HS, set its
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value to default to properly account for the case when it's not allocated.
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`ALES_PRESENT[{2,5}]' are treated this way in the code below: 0 means that
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the syllable has been neither marked in HS, nor allocated; 1 - marked in
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HS, but not allocated; 2 - not marked in HS, but allocated; 3 - both marked
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in HS and allocated. */
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if (hs & (0x1 << 25))
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{
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instr->ales_present[5] = 1;
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instr->ales[5] = 0x01c0;
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}
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if (hs & (0x1 << 22))
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{
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instr->ales_present[2] = 1;
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instr->ales[2] = 0x01c0;
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}
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/* Calculate the size of f1 fragment in bytes. For a valid instruction it
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should be equal to either of `pos', `pos + 4' or `pos + 8'. What should I
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do if it's not? */
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mdl = ((hs & 0xf) + 1) * 4;
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/* The following condition means that ALES{2,5} are physically present within
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the wide instruction. However, they should be probably taken into account
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only if HS.ale{2,5} are set. Should I disassemble them if these bits are
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not set but the syllables physically exist? */
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if (((hs & (0x1 << 15)) && mdl == pos + 8)
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|| (!(hs & (0x1 << 15)) && mdl == pos + 4))
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{
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/* Fill in ALES5 and ALES2 syllables even if none of them is specified in
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HS as present. This will let me output this syllable into disassembly
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whichever case takes place. */
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instr->ales[5] = translator_lduw(env, &ctx->base, pos);
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instr->ales[2] = translator_lduw(env, &ctx->base, pos + 2);
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/* Adjust `ALES_PRESENT[{5,2}]' as proposed above now that we know that
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they are allocated. */
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instr->ales_present[5] |= 0x2;
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instr->ales_present[2] |= 0x2;
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pos += 4;
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}
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/* Check for CS1. */
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if (hs & (0x1 << 15))
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{
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instr->cs1_present = 1;
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instr->cs1 = translator_ldl(env, &ctx->base, pos);
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pos += 4;
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}
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/* A primitive control just for a moment. */
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if (mdl != pos)
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{
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/* This is either an APB instruction or an invalid one. Let's stupidly
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believe that the former takes place and signalize our caller about
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that by returning 0. */
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return next_pc;
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}
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/* Check for ALES{0,1,3,4}. */
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for (i = 0; i < 5; i++)
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{
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if (i == 2)
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continue;
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if (hs & (0x1 << (20 + i)))
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{
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instr->ales_present[i] = 1;
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/* Recall the idiotic order of half-syllables in the packed wide
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instruction. */
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instr->ales[i] = translator_lduw(env,
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pos + 2 * ((hsyll_cntr & ~0x1) + 1 - (hsyll_cntr & 0x1)));
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hsyll_cntr++;
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}
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}
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/* Check for AASj half-syllables. To encode them SS syllable of SF1 type
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should be present. */
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if (instr->ss_present && (instr->ss & (0x1 << 20)) == 0)
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{
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for (i = 0; i < 4; i++)
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{
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if (instr->ss & (0x1 << (12 + i)))
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{
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instr->aas_present[i >> 1] = 1;
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instr->aas_present[2 + i] = 1;
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}
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}
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for (i = 0; i < 6; i++)
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{
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if (instr->aas_present[i])
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{
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/* Recall the idiotic order of half-syllables in the packed wide
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instruction. Note that the first AAS half-syllable may share a
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syllable with the last ALES. */
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instr->aas[i] = translator_lduw(env,
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pos + 2 * ((hsyll_cntr & ~0x1) + 1 - (hsyll_cntr & 0x1)));
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hsyll_cntr++;
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}
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}
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}
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if (hsyll_cntr & 0x1)
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{
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/* Simplify the calculation of offset in BUF[] a bit by taking the above
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condition into account. */
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instr->half_gap = translator_lduw(env, pos + 2 * (hsyll_cntr & ~0x1));
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instr->half_gap_present = 1;
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/* Ensure that hsyll_cntr is even. This is implied when calculating GAP
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below. */
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hsyll_cntr++;
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}
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/* Calculate the next 32-bit syllable's position. It may be the uppermost LTS
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syllable. Note that I don't consider the case when LTS syllables reuse the
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values encoded in the preceding ones, though according to `iset-v5.single'
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this is quite legal. GAS doesn't produce such a code. Hopefully neither LAS
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has ever done that . . . */
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gap = pos + 2 * hsyll_cntr;
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/* Set POS to point to the last syllable in the current wide instruction and
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extract CDSj and PLSj syllables if any. */
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pos = ((((hs & 0x70) >> 4) + 1) << 3) - 4;
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/* Check for CDSj syllables. */
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for (i = 0; i < ((hs & 0x30000) >> 16); i++)
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{
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instr->cds_present[i] = 1;
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instr->cds[i] = translator_ldl(env, &ctx->base, pos);
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pos -= 4;
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}
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/* Check for PLSj syllables. */
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for (i = 0; i < ((hs & 0xc0000) >> 18); i++)
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{
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instr->pls_present[i] = 1;
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instr->pls[i] = translator_ldl(env, &ctx->base, pos);
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pos -= 4;
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}
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/* Now POS should point to the lowermost LTS0 syllable if any. If there are
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no LTSj syllables in this instruction, POS should point to the last
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syllable consisting of half-syllables.
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If neither of these conditions holds true, believe that it's not a valid
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synchronous instruction by analogy with the middle point test above.
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Engineers are said to customize instructions with references to missing
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literal syllables occasionally, but the lack of space for more substantial
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syllables should not be allowed for. */
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if (pos < gap && pos != gap - 4)
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return next_pc;
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/* Extract available LTSj syllables. */
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for (i = 0; i < 4 && pos >= gap; i++)
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{
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instr->lts_present[i] = 1;
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instr->lts[i] = translator_ldl(env, &ctx->base, pos);
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pos -= 4;
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}
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/* It makes sense to enumerate GAP syllables in a normal order unlike LTS
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ones. */
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for (i = 0; i < 16 && gap <= pos; i++)
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{
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instr->gap_present[i] = 1;
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instr->gap[i] = translator_ldl(env, &ctx->base, gap);
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gap += 4;
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}
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return next_pc;
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}
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static target_ulong disas_e2k_insn(DisasContext *dc, CPUState *cs)
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{
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E2KCPU *cpu = E2K_CPU(cs);
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CPUE2KState *env = &cpu->env;
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struct unpacked_instr *instr = &unpacked_instr;
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target_ulong next_pc = unpack_instr(env, dc, dc->base.pc_next, instr);
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// TODO: gen ops
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qemu_log_mask(LOG_UNIMP, "disas_e2k_insn: not implemented, ip 0x%lx, HS 0x%x\n",
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dc->base.pc_next, instr->hs);
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return next_pc;
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}
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static void e2k_tr_init_disas_context(DisasContextBase *db, CPUState *cs)
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{
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DisasContext *dc = container_of(db, DisasContext, base);
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dc->pc = dc->base.pc_first;
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dc->npc = dc->base.pc_next;
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}
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static void e2k_tr_tb_start(DisasContextBase *db, CPUState *cs)
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{
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// TODO
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qemu_log_mask(LOG_UNIMP, "e2k_tr_tb_start: not implemented\n");
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}
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static void e2k_tr_insn_start(DisasContextBase *db, CPUState *cs)
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{
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DisasContext *dc = container_of(db, DisasContext, base);
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tcg_gen_insn_start(dc->pc);
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// FIXME: stop decoding on page boundary?
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}
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static bool e2k_tr_breakpoint_check(DisasContextBase *db, CPUState *cs,
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const CPUBreakpoint *bp)
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{
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// TODO
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qemu_log_mask(LOG_UNIMP, "e2k_tr_breakpoint_check: not implemented\n");
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return false;
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}
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static void e2k_tr_translate_insn(DisasContextBase *db, CPUState *cs)
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{
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DisasContext *dc = container_of(db, DisasContext, base);
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dc->base.pc_next = disas_e2k_insn(dc, cs);
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}
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static void e2k_tr_tb_stop(DisasContextBase *db, CPUState *cs)
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{
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// TODO
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qemu_log_mask(LOG_UNIMP, "e2k_tr_tb_stop: not implemented\n");
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}
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static void e2k_tr_disas_log(const DisasContextBase *db, CPUState *cpu)
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{
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// TODO
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qemu_log_mask(LOG_UNIMP, "e2k_tr_disas_log: not implemented\n");
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}
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static const TranslatorOps e2k_tr_ops = {
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.init_disas_context = e2k_tr_init_disas_context,
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.tb_start = e2k_tr_tb_start,
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.insn_start = e2k_tr_insn_start,
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.breakpoint_check = e2k_tr_breakpoint_check,
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.translate_insn = e2k_tr_translate_insn,
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.tb_stop = e2k_tr_tb_stop,
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.disas_log = e2k_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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{
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DisasContext dc = {};
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translator_loop(&e2k_tr_ops, &dc.base, cs, tb, max_insns);
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}
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void restore_state_to_opc(CPUE2KState *env, TranslationBlock *tb,
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target_ulong *data)
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{
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// TODO
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qemu_log_mask(LOG_UNIMP, "restore_state_to_opc: not implemented\n");
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}
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void e2k_tcg_initialize(void) {
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// TODO
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qemu_log_mask(LOG_UNIMP, "e2k_tcg_initialize: not implemented\n");
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}
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