qemu-e2k/target/riscv
Xu Lu 5cb0e7abe1 target/riscv: Fix mcycle/minstret increment behavior
The mcycle/minstret counter's stop flag is mistakenly updated on a copy
on stack. Thus the counter increments even when the CY/IR bit in the
mcountinhibit register is set. This commit corrects its behavior.

Fixes: 3780e33732 (target/riscv: Support mcycle/minstret write operation)
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-05 22:28:54 +03:00
..
insn_trans
kvm target/riscv/kvm: do not use non-portable strerrorname_np() 2023-12-23 19:29:56 +03:00
tcg target/riscv: don't verify ISA compatibility for zicntr and zihpm 2023-11-22 13:56:13 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h
cpu_cfg.h target/riscv: Add "pmu-mask" property to replace "pmu-num" 2023-11-07 11:06:02 +10:00
cpu_helper.c target/riscv/cpu_helper.c: Fix mxr bit behavior 2023-11-22 14:03:37 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
cpu.c target: Use generic cpu_model_from_type() 2024-01-05 16:20:14 +01:00
cpu.h target/riscv: Use generic cpu_list() 2024-01-05 16:20:14 +01:00
crypto_helper.c
csr.c target/riscv: Fix mcycle/minstret increment behavior 2024-01-05 22:28:54 +03:00
debug.c
debug.h
fpu_helper.c
gdbstub.c
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h target/riscv: Use env_archcpu() in [check_]nanbox() 2023-11-07 12:13:27 +01:00
Kconfig
m128_helper.c
machine.c target/riscv: Constify VMState in machine.c 2023-12-29 11:17:30 +11:00
meson.build
monitor.c
op_helper.c
pmp.c
pmp.h
pmu.c target/riscv: Add "pmu-mask" property to replace "pmu-num" 2023-11-07 11:06:02 +10:00
pmu.h
riscv-qmp-cmds.c target: Use generic cpu_model_from_type() 2024-01-05 16:20:14 +01:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c
vcrypto_helper.c
vector_helper.c
vector_internals.c
vector_internals.h
xthead.decode
XVentanaCondOps.decode
zce_helper.c