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Rollup merge of #47826 - gnzlbg:patch-2, r=alexcrichton

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Whitelist v7 feature for ARM and AARCH64.

Needed for `v7` features in `coresimd`.

See b2f7be24d5/coresimd/src/arm/v7.rs (L40) which used to work but doesn't anymore.

r? alexcrichton
This commit is contained in:
kennytm 2018-01-30 17:10:56 +08:00 committed by GitHub
commit 16d3fdb752
1 changed files with 2 additions and 2 deletions
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4
src/librustc_trans/llvm_util.rs
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@ -79,9 +79,9 @@ unsafe fn configure_llvm(sess: &Session) {
// detection code will walk past the end of the feature array, // detection code will walk past the end of the feature array,
// leading to crashes. // leading to crashes.
const ARM_WHITELIST: &'static [&'static str] = &["neon\0", "vfp2\0", "vfp3\0", "vfp4\0"]; const ARM_WHITELIST: &'static [&'static str] = &["neon\0", "v7\0", "vfp2\0", "vfp3\0", "vfp4\0"];
const AARCH64_WHITELIST: &'static [&'static str] = &["neon\0"]; const AARCH64_WHITELIST: &'static [&'static str] = &["neon\0", "v7\0"];
const X86_WHITELIST: &'static [&'static str] = &["avx\0", "avx2\0", "bmi\0", "bmi2\0", "sse\0", const X86_WHITELIST: &'static [&'static str] = &["avx\0", "avx2\0", "bmi\0", "bmi2\0", "sse\0",
"sse2\0", "sse3\0", "sse4.1\0", "sse4.2\0", "sse2\0", "sse3\0", "sse4.1\0", "sse4.2\0",