Auto merge of #43711 - lu-zero:master, r=nagisa
More Altivec intrinsics Beside the usual json + generated files, I added two additional modifiers in the generator.
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@ -19,7 +19,7 @@ import itertools
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SPEC = re.compile(
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r'^(?:(?P<void>V)|(?P<id>[iusfIUSF])(?:\((?P<start>\d+)-(?P<end>\d+)\)|'
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r'(?P<width>\d+)(:?/(?P<llvm_width>\d+))?)'
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r'|(?P<reference>\d+))(?P<index>\.\d+)?(?P<modifiers>[vShdnwusfDMC]*)(?P<force_width>x\d+)?'
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r'|(?P<reference>\d+))(?P<index>\.\d+)?(?P<modifiers>[vShdnwusfDMCNW]*)(?P<force_width>x\d+)?'
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r'(?:(?P<pointer>Pm|Pc)(?P<llvm_pointer>/.*)?|(?P<bitcast>->.*))?$'
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)
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@ -246,6 +246,12 @@ class Vector(Type):
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return Vector(self._elem, self._length // 2)
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elif spec == 'd':
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return Vector(self._elem, self._length * 2)
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elif spec == 'N':
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elem = self._elem.__class__(self._elem.bitwidth() // 2)
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return Vector(elem, self._length * 2)
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elif spec == 'W':
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elem = self._elem.__class__(self._elem.bitwidth() * 2)
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return Vector(elem, self._length // 2)
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elif spec.startswith('x'):
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new_bitwidth = int(spec[1:])
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return Vector(self._elem, new_bitwidth // self._elem.bitwidth())
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@ -714,6 +720,8 @@ def parse_args():
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- 'd': double the length of the vector (u32x2 -> u32x4)
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- 'n': narrow the element of the vector (u32x4 -> u16x4)
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- 'w': widen the element of the vector (u16x4 -> u32x4)
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- 'N': half the length of the vector element (u32x4 -> u16x8)
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- 'W': double the length of the vector element (u16x8 -> u32x4)
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- 'u': force a number (vector or scalar) to be unsigned int (f32x4 -> u32x4)
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- 's': force a number (vector or scalar) to be signed int (u32x4 -> i32x4)
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- 'f': force a number (vector or scalar) to be float (u32x4 -> f32x4)
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@ -72,6 +72,55 @@
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"llvm": "vmin{0.kind}{0.data_type_short}",
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"ret": "i(8-32)",
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"args": ["0", "0"]
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},
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{
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"intrinsic": "sub{0.kind}{0.data_type_short}s",
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"width": [128],
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"llvm": "vsub{0.kind}{0.data_type_short}s",
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"ret": "i(8-32)",
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"args": ["0", "0"]
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},
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{
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"intrinsic": "subc",
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"width": [128],
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"llvm": "vsubcuw",
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"ret": "u32",
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"args": ["0", "0"]
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},
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{
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"intrinsic": "add{0.kind}{0.data_type_short}s",
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"width": [128],
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"llvm": "vadd{0.kind}{0.data_type_short}s",
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"ret": "i(8-32)",
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"args": ["0", "0"]
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},
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{
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"intrinsic": "addc",
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"width": [128],
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"llvm": "vaddcuw",
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"ret": "u32",
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"args": ["0", "0"]
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},
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{
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"intrinsic": "mule{1.kind}{1.data_type_short}",
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"width": [128],
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"llvm": "vmule{0.kind}{1.data_type_short}",
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"ret": "i(16-32)",
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"args": ["0N", "1"]
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},
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{
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"intrinsic": "mulo{1.kind}{1.data_type_short}",
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"width": [128],
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"llvm": "vmulo{0.kind}{1.data_type_short}",
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"ret": "i(16-32)",
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"args": ["0N", "1"]
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},
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{
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"intrinsic": "avg{0.kind}{0.data_type_short}",
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"width": [128],
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"llvm": "vavg{0.kind}{0.data_type_short}",
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"ret": "i(8-32)",
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"args": ["0", "0"]
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}
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]
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}
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@ -142,6 +142,146 @@ pub fn find(name: &str) -> Option<Intrinsic> {
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output: &::U32x4,
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definition: Named("llvm.ppc.altivec.vminuw")
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},
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"_vec_subsbs" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
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output: &::I8x16,
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definition: Named("llvm.ppc.altivec.vsubsbs")
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},
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"_vec_sububs" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
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output: &::U8x16,
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definition: Named("llvm.ppc.altivec.vsububs")
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},
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"_vec_subshs" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
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output: &::I16x8,
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definition: Named("llvm.ppc.altivec.vsubshs")
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},
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"_vec_subuhs" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
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output: &::U16x8,
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definition: Named("llvm.ppc.altivec.vsubuhs")
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},
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"_vec_subsws" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
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output: &::I32x4,
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definition: Named("llvm.ppc.altivec.vsubsws")
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},
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"_vec_subuws" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
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output: &::U32x4,
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definition: Named("llvm.ppc.altivec.vsubuws")
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},
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"_vec_subc" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
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output: &::U32x4,
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definition: Named("llvm.ppc.altivec.vsubcuw")
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},
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"_vec_addsbs" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
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output: &::I8x16,
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definition: Named("llvm.ppc.altivec.vaddsbs")
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},
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"_vec_addubs" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
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output: &::U8x16,
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definition: Named("llvm.ppc.altivec.vaddubs")
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},
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"_vec_addshs" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
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output: &::I16x8,
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definition: Named("llvm.ppc.altivec.vaddshs")
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},
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"_vec_adduhs" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
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output: &::U16x8,
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definition: Named("llvm.ppc.altivec.vadduhs")
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},
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"_vec_addsws" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
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output: &::I32x4,
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definition: Named("llvm.ppc.altivec.vaddsws")
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},
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"_vec_adduws" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
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output: &::U32x4,
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definition: Named("llvm.ppc.altivec.vadduws")
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},
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"_vec_addc" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
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output: &::U32x4,
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definition: Named("llvm.ppc.altivec.vaddcuw")
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},
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"_vec_mulesb" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
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output: &::I16x8,
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definition: Named("llvm.ppc.altivec.vmulesb")
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},
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"_vec_muleub" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
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output: &::U16x8,
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definition: Named("llvm.ppc.altivec.vmuleub")
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},
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"_vec_mulesh" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
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output: &::I32x4,
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definition: Named("llvm.ppc.altivec.vmulesh")
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},
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"_vec_muleuh" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
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output: &::U32x4,
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definition: Named("llvm.ppc.altivec.vmuleuh")
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},
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"_vec_mulosb" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
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output: &::I16x8,
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definition: Named("llvm.ppc.altivec.vmulosb")
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},
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"_vec_muloub" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
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output: &::U16x8,
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definition: Named("llvm.ppc.altivec.vmuloub")
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},
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"_vec_mulosh" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
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output: &::I32x4,
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definition: Named("llvm.ppc.altivec.vmulosh")
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},
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"_vec_mulouh" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
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output: &::U32x4,
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definition: Named("llvm.ppc.altivec.vmulouh")
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},
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"_vec_avgsb" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
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output: &::I8x16,
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definition: Named("llvm.ppc.altivec.vavgsb")
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},
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"_vec_avgub" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
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output: &::U8x16,
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definition: Named("llvm.ppc.altivec.vavgub")
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},
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"_vec_avgsh" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
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output: &::I16x8,
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definition: Named("llvm.ppc.altivec.vavgsh")
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},
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"_vec_avguh" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
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output: &::U16x8,
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definition: Named("llvm.ppc.altivec.vavguh")
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},
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"_vec_avgsw" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
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output: &::I32x4,
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definition: Named("llvm.ppc.altivec.vavgsw")
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},
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"_vec_avguw" => Intrinsic {
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inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
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output: &::U32x4,
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definition: Named("llvm.ppc.altivec.vavguw")
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},
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_ => return None,
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})
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}
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