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Enable building the LLVM Hexagon target

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This commit is contained in:
Michael Wu 2017-04-18 16:23:47 -04:00
parent 27b00ec752
commit 22eb3c69b9
2 changed files with 2 additions and 2 deletions
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2
src/bootstrap/config.toml.example
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@ -51,7 +51,7 @@
# support. You'll need to write a target specification at least, and most # support. You'll need to write a target specification at least, and most
# likely, teach rustc about the C ABI of the target. Get in touch with the # likely, teach rustc about the C ABI of the target. Get in touch with the
# Rust team and file an issue if you need assistance in porting! # Rust team and file an issue if you need assistance in porting!
#targets = "X86;ARM;AArch64;Mips;PowerPC;SystemZ;JSBackend;MSP430;Sparc;NVPTX" #targets = "X86;ARM;AArch64;Mips;PowerPC;SystemZ;JSBackend;MSP430;Sparc;NVPTX;Hexagon"
# Cap the number of parallel linker invocations when compiling LLVM. # Cap the number of parallel linker invocations when compiling LLVM.
# This can be useful when building LLVM with debug info, which significantly # This can be useful when building LLVM with debug info, which significantly

2
src/bootstrap/native.rs
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@ -81,7 +81,7 @@ pub fn llvm(build: &Build, target: &str) {
// NOTE: remember to also update `config.toml.example` when changing the defaults! // NOTE: remember to also update `config.toml.example` when changing the defaults!
let llvm_targets = match build.config.llvm_targets { let llvm_targets = match build.config.llvm_targets {
Some(ref s) => s, Some(ref s) => s,
None => "X86;ARM;AArch64;Mips;PowerPC;SystemZ;JSBackend;MSP430;Sparc;NVPTX", None => "X86;ARM;AArch64;Mips;PowerPC;SystemZ;JSBackend;MSP430;Sparc;NVPTX;Hexagon",
}; };
let assertions = if build.config.llvm_assertions {"ON"} else {"OFF"}; let assertions = if build.config.llvm_assertions {"ON"} else {"OFF"};