Add safe wrapper for atomic_singlethreadfence_*
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@ -1572,6 +1572,47 @@ pub fn fence(order: Ordering) {
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}
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/// A compiler memory barrier.
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///
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/// `compiler_barrier` does not emit any machine code, but prevents the compiler from re-ordering
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/// memory operations across this point. Which reorderings are disallowed is dictated by the given
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/// [`Ordering`]. Note that `compiler_barrier` does *not* introduce inter-thread memory
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/// synchronization; for that, a [`fence`] is needed.
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///
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/// The re-ordering prevented by the different ordering semantics are:
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///
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/// - with [`SeqCst`], no re-ordering of reads and writes across this point is allowed.
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/// - with [`Release`], preceding reads and writes cannot be moved past subsequent writes.
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/// - with [`Acquire`], subsequent reads and writes cannot be moved ahead of preceding reads.
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/// - with [`AcqRel`], both of the above rules are enforced.
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///
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/// # Panics
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///
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/// Panics if `order` is [`Relaxed`].
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///
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/// [`fence`]: fn.fence.html
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/// [`Ordering`]: enum.Ordering.html
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/// [`Acquire`]: enum.Ordering.html#variant.Acquire
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/// [`SeqCst`]: enum.Ordering.html#variant.SeqCst
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/// [`Release`]: enum.Ordering.html#variant.Release
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/// [`AcqRel`]: enum.Ordering.html#variant.AcqRel
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/// [`Relaxed`]: enum.Ordering.html#variant.Relaxed
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#[inline]
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#[unstable(feature = "std_compiler_fences", issue = "41091")]
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pub fn compiler_barrier(order: Ordering) {
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unsafe {
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match order {
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Acquire => intrinsics::atomic_singlethreadfence_acq(),
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Release => intrinsics::atomic_singlethreadfence_rel(),
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AcqRel => intrinsics::atomic_singlethreadfence_acqrel(),
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SeqCst => intrinsics::atomic_singlethreadfence(),
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Relaxed => panic!("there is no such thing as a relaxed barrier"),
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__Nonexhaustive => panic!("invalid memory ordering"),
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}
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}
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}
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#[cfg(target_has_atomic = "8")]
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#[stable(feature = "atomic_debug", since = "1.3.0")]
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impl fmt::Debug for AtomicBool {
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