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Define AVX conversion intrinsics

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This defines the following intrinsics:

 * `_mm256_cvtepi32_pd`
 * `_mm256_cvtepi32_ps`
 * `_mm256_cvtpd_epi32`
 * `_mm256_cvtpd_ps`
 * `_mm256_cvtps_epi32`
 * `_mm256_cvtps_pd`
 * `_mm256_cvttpd_epi32`
 * `_mm256_cvttps_epi32`

Intel reference: https://software.intel.com/en-us/node/514130.
This commit is contained in:
Ruud van Asseldonk 2016-03-08 22:36:54 +01:00
parent 37efeae886
commit 51b5300b3f
1 changed files with 56 additions and 0 deletions
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56
src/etc/platform-intrinsics/x86/avx.json
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@ -15,6 +15,62 @@
"ret": "f(32-64)",
"args": ["s8SPc"]
},
{
"intrinsic": "256_cvtepi32_pd",
"width": [256],
"llvm": "cvtdq2.pd.256",
"ret": "f64",
"args": ["s32h"]
},
{
"intrinsic": "256_cvtepi32_ps",
"width": [256],
"llvm": "cvtdq2.ps.256",
"ret": "f32",
"args": ["s32"]
},
{
"intrinsic": "256_cvtpd_epi32",
"width": [256],
"llvm": "cvt.pd2dq.256",
"ret": "s32h",
"args": ["f64"]
},
{
"intrinsic": "256_cvtpd_ps",
"width": [256],
"llvm": "cvt.pd2.ps.256",
"ret": "f32h",
"args": ["f64"]
},
{
"intrinsic": "256_cvtps_epi32",
"width": [256],
"llvm": "cvt.ps2dq.256",
"ret": "s32",
"args": ["f32"]
},
{
"intrinsic": "256_cvtps_pd",
"width": [256],
"llvm": "cvt.ps2.pd.256",
"ret": "f64",
"args": ["f32h"]
},
{
"intrinsic": "256_cvttpd_epi32",
"width": [256],
"llvm": "cvtt.pd2dq.256",
"ret": "s32h",
"args": ["f64"]
},
{
"intrinsic": "256_cvttps_epi32",
"width": [256],
"llvm": "cvtt.ps2dq.256",
"ret": "s32",
"args": ["f32"]
},
{
"intrinsic": "256_dp_ps",
"width": [256],