diff --git a/src/intrinsics.rs b/src/intrinsics.rs index a2451ff464b..5c7f8b46f5c 100644 --- a/src/intrinsics.rs +++ b/src/intrinsics.rs @@ -121,6 +121,7 @@ fn lane_type_and_count<'tcx>( layout: TyLayout<'tcx>, intrinsic: &str, ) -> (TyLayout<'tcx>, usize) { + assert!(layout.ty.is_simd()); let lane_count = match layout.fields { layout::FieldPlacement::Array { stride: _, count } => usize::try_from(count).unwrap(), _ => panic!("Non vector type {:?} passed to or returned from simd_* intrinsic {}", layout.ty, intrinsic), @@ -805,6 +806,26 @@ pub fn codegen_intrinsic_call<'a, 'tcx: 'a>( simd_cmp!(fx, intrinsic, UnsignedGreaterThanOrEqual|SignedGreaterThanOrEqual(x, y) -> ret); }; + // simd_shuffle32(x: T, y: T, idx: [u32; 32]) -> U + _ if intrinsic.starts_with("simd_shuffle"), (c x, c y, c idx) { + let n: usize = intrinsic["simd_shuffle".len()..].parse().unwrap(); + + assert_eq!(x.layout(), y.layout()); + let layout = x.layout(); + + let (lane_type, lane_count) = lane_type_and_count(fx, layout, intrinsic); + let (ret_lane_type, ret_lane_count) = lane_type_and_count(fx, ret.layout(), intrinsic); + + assert_eq!(lane_type, ret_lane_type); + assert_eq!(n, ret_lane_count); + + let total_len = lane_count * 2; + + // TODO get shuffle indices + fx.tcx.sess.warn("simd_shuffle* not yet implemented"); + crate::trap::trap_unimplemented(fx, "simd_shuffle* not yet implemented"); + }; + simd_add, (c x, c y) { simd_binop!(fx, intrinsic, iadd(x, y) -> ret); }; @@ -832,7 +853,7 @@ pub fn codegen_intrinsic_call<'a, 'tcx: 'a>( simd_or, (c x, c y) { simd_binop!(fx, intrinsic, bor(x, y) -> ret); }; - simd_bxor, (c x, c y) { + simd_xor, (c x, c y) { simd_binop!(fx, intrinsic, bxor(x, y) -> ret); }; diff --git a/src/llvm_intrinsics.rs b/src/llvm_intrinsics.rs index 63627c41a2c..765adafa10b 100644 --- a/src/llvm_intrinsics.rs +++ b/src/llvm_intrinsics.rs @@ -19,3 +19,11 @@ pub fn codegen_llvm_intrinsic_call<'a, 'tcx: 'a>( trap_unreachable(fx, "[corruption] Diverging intrinsic returned."); } } + +// llvm.x86.sse2.pmovmskb.128 +// llvm.x86.avx2.vperm2i128 +// llvm.x86.ssse3.pshuf.b.128 +// llvm.x86.avx2.pshuf.b +// llvm.x86.avx2.pmovmskb +// llvm.x86.avx2.psrli.w +// llvm.x86.sse2.psrli.w