Use hashtable rather than bitset for vreg constraints in ra; speeds compilation.
This commit is contained in:
Graydon Hoare
parent
a9e2327a18
commit
79dc07d648
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@ -118,7 +118,7 @@ type abi =
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abi_str_of_hardreg: (int -> string);
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abi_emit_target_specific: (Il.emitter -> Il.quad -> unit);
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abi_constrain_vregs: (Il.quad -> Bits.t array -> unit);
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abi_constrain_vregs: (Il.quad -> (Il.vreg,Bits.t) Hashtbl.t -> unit);
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abi_emit_fn_prologue: (Il.emitter
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-> Common.size (* framesz *)
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@ -324,11 +324,11 @@ let dump_quads cx =
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let calculate_vreg_constraints
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(cx:ctxt)
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(constraints:Bits.t array)
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(constraints:(Il.vreg,Bits.t) Hashtbl.t)
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(q:quad)
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: unit =
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let abi = cx.ctxt_abi in
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Array.iter (fun c -> Bits.clear c; Bits.invert c) constraints;
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Hashtbl.clear constraints;
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abi.Abi.abi_constrain_vregs q constraints;
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iflog cx
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begin
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@ -341,9 +341,12 @@ let calculate_vreg_constraints
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match r with
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Il.Hreg _ -> ()
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| Il.Vreg v ->
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let hregs = Bits.to_list constraints.(v) in
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log cx "<v%d> constrained to hregs: [%s]"
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v (list_to_str hregs hr_str)
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match htab_search constraints v with
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None -> log cx "<v%d> unconstrained" v
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| Some c ->
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let hregs = Bits.to_list c in
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log cx "<v%d> constrained to hregs: [%s]"
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v (list_to_str hregs hr_str)
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end;
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r
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in
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@ -376,10 +379,9 @@ let reg_alloc
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let (live_in_vregs, live_out_vregs) =
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calculate_live_bitvectors cx
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in
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let n_vregs = cx.ctxt_n_vregs in
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let n_hregs = abi.Abi.abi_n_hardregs in
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let (vreg_constraints:Bits.t array) = (* vreg idx -> hreg bits.t *)
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Array.init n_vregs (fun _ -> Bits.create n_hregs true)
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(* vreg idx -> hreg bits.t *)
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let (vreg_constraints:(Il.vreg,Bits.t) Hashtbl.t) =
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Hashtbl.create 0
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in
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let inactive_hregs = ref [] in (* [hreg] *)
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let active_hregs = ref [] in (* [hreg] *)
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@ -497,6 +499,13 @@ let reg_alloc
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else ()
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in
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let get_vreg_constraints v =
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match htab_search vreg_constraints v with
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None -> all_hregs
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| Some c -> c
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in
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let use_vreg def i vreg =
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if Hashtbl.mem vreg_to_hreg vreg
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then
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@ -508,18 +517,19 @@ let reg_alloc
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end
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else
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let hreg =
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let constrs = vreg_constraints.(vreg) in
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match select_constrained constrs (!inactive_hregs) with
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None ->
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let h = spill_constrained constrs i in
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iflog cx
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(fun _ -> log cx "selected %s to spill and use for <v%d>"
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(hr_str h) vreg);
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let constrs = get_vreg_constraints vreg in
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match select_constrained constrs (!inactive_hregs) with
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None ->
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let h = spill_constrained constrs i in
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iflog cx
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(fun _ ->
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log cx "selected %s to spill and use for <v%d>"
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(hr_str h) vreg);
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h
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| Some h ->
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iflog cx (fun _ -> log cx "selected inactive %s for <v%d>"
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(hr_str h) vreg);
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h
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| Some h ->
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iflog cx (fun _ -> log cx "selected inactive %s for <v%d>"
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(hr_str h) vreg);
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h
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in
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inactive_hregs :=
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List.filter (fun x -> x != hreg) (!inactive_hregs);
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@ -569,7 +579,7 @@ let reg_alloc
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* This is awful but it saves us from cached/constrained
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* interference as was found in issue #152. *)
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if List.exists
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(fun v -> not (Bits.equal vreg_constraints.(v) all_hregs))
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(fun v -> not (Bits.equal (get_vreg_constraints v) all_hregs))
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used
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then
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begin
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@ -577,7 +587,7 @@ let reg_alloc
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spill_all_regs i;
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(* Check for over-constrained-ness after any such regfence. *)
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let vreg_constrs v =
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(v, Bits.to_list (vreg_constraints.(v)))
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(v, Bits.to_list (get_vreg_constraints v))
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in
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let constrs = List.map vreg_constrs (used @ defined) in
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let constrs_collide (v1,c1) =
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@ -385,7 +385,7 @@ let emit_target_specific
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;;
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let constrain_vregs (q:Il.quad) (hregs:Bits.t array) : unit =
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let constrain_vregs (q:Il.quad) (hregs:(Il.vreg,Bits.t) Hashtbl.t) : unit =
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let involves_8bit_cell =
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let b = ref false in
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@ -402,6 +402,10 @@ let constrain_vregs (q:Il.quad) (hregs:Bits.t array) : unit =
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!b
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in
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let get_hregs v =
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htab_search_or_add hregs v (fun _ -> Bits.create n_hardregs true)
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in
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let qp_mem _ m = m in
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let qp_cell _ c =
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begin
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@ -409,7 +413,7 @@ let constrain_vregs (q:Il.quad) (hregs:Bits.t array) : unit =
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Il.Reg (Il.Vreg v, _) when involves_8bit_cell ->
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(* 8-bit register cells must only be al, cl, dl, bl.
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* Not esi/edi. *)
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let hv = hregs.(v) in
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let hv = get_hregs v in
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List.iter (fun bad -> Bits.set hv bad false) [esi; edi]
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| _ -> ()
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end;
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@ -425,7 +429,7 @@ let constrain_vregs (q:Il.quad) (hregs:Bits.t array) : unit =
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begin
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match b.Il.binary_rhs with
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Il.Cell (Il.Reg (Il.Vreg v, _)) ->
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let hv = hregs.(v) in
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let hv = get_hregs v in
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(* Shift src has to be ecx. *)
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List.iter
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(fun bad -> Bits.set hv bad false)
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