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rustbuild: WebAssembly is no longer an experimental LLVM backend

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This commit is contained in:
Sam Elliott 2019-08-02 17:05:59 +01:00
parent 184fb08037
commit 9cb948feea
2 changed files with 5 additions and 6 deletions
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7
config.toml.example
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@ -57,14 +57,13 @@
# support. You'll need to write a target specification at least, and most # support. You'll need to write a target specification at least, and most
# likely, teach rustc about the C ABI of the target. Get in touch with the # likely, teach rustc about the C ABI of the target. Get in touch with the
# Rust team and file an issue if you need assistance in porting! # Rust team and file an issue if you need assistance in porting!
#targets = "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;X86" #targets = "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86"
# LLVM experimental targets to build support for. These targets are specified in # LLVM experimental targets to build support for. These targets are specified in
# the same format as above, but since these targets are experimental, they are # the same format as above, but since these targets are experimental, they are
# not built by default and the experimental Rust compilation targets that depend # not built by default and the experimental Rust compilation targets that depend
# on them will not work unless the user opts in to building them. By default the # on them will not work unless the user opts in to building them.
# `WebAssembly` target is enabled when compiling LLVM from scratch. #experimental-targets = ""
#experimental-targets = "WebAssembly"
# Cap the number of parallel linker invocations when compiling LLVM. # Cap the number of parallel linker invocations when compiling LLVM.
# This can be useful when building LLVM with debug info, which significantly # This can be useful when building LLVM with debug info, which significantly

4
src/bootstrap/native.rs
View File

@ -125,7 +125,7 @@ impl Step for Llvm {
} else { } else {
match builder.config.llvm_targets { match builder.config.llvm_targets {
Some(ref s) => s, Some(ref s) => s,
None => "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;X86", None => "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86",
} }
}; };
@ -134,7 +134,7 @@ impl Step for Llvm {
} else { } else {
match builder.config.llvm_experimental_targets { match builder.config.llvm_experimental_targets {
Some(ref s) => s, Some(ref s) => s,
None => "WebAssembly", None => "",
} }
}; };