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Add intrinsics & target features for rd{rand,seed}

This commit is contained in:
Simonas Kazlauskas 2016-12-22 23:53:30 +02:00
parent 17d873c2db
commit b2cf6df875
4 changed files with 85 additions and 1 deletions
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27
src/etc/platform-intrinsics/x86/rdrand.json Normal file
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@ -0,0 +1,27 @@
{
"intrinsic_prefix": "_rdrand",
"llvm_prefix": "llvm.x86.rdrand.",
"intrinsics": [
{
"intrinsic": "16_step",
"width": ["0"],
"llvm": "16",
"ret": "(U16,S32)",
"args": []
},
{
"intrinsic": "32_step",
"width": ["0"],
"llvm": "32",
"ret": "(U32,S32)",
"args": []
},
{
"intrinsic": "64_step",
"width": ["0"],
"llvm": "64",
"ret": "(U64,S32)",
"args": []
}
]
}

27
src/etc/platform-intrinsics/x86/rdseed.json Normal file
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@ -0,0 +1,27 @@
{
"intrinsic_prefix": "_rdseed",
"llvm_prefix": "llvm.x86.rdseed.",
"intrinsics": [
{
"intrinsic": "16_step",
"width": ["0"],
"llvm": "16",
"ret": "(U16,S32)",
"args": []
},
{
"intrinsic": "32_step",
"width": ["0"],
"llvm": "32",
"ret": "(U32,S32)",
"args": []
},
{
"intrinsic": "64_step",
"width": ["0"],
"llvm": "64",
"ret": "(U64,S32)",
"args": []
}
]
}

2
src/librustc_driver/target_features.rs
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@ -25,7 +25,7 @@ const ARM_WHITELIST: &'static [&'static str] = &["neon\0", "vfp2\0", "vfp3\0", "
const X86_WHITELIST: &'static [&'static str] = &["avx\0", "avx2\0", "bmi\0", "bmi2\0", "sse\0",
"sse2\0", "sse3\0", "sse4.1\0", "sse4.2\0",
"ssse3\0", "tbm\0", "lzcnt\0", "popcnt\0",
"sse4a\0"];
"sse4a\0", "rdrnd\0", "rdseed\0"];
/// Add `target_feature = "..."` cfgs for a variety of platform
/// specific features (SSE, NEON etc.).

30
src/librustc_platform_intrinsics/x86.rs
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@ -872,6 +872,36 @@ pub fn find(name: &str) -> Option<Intrinsic> {
output: &::F64x4,
definition: Named("llvm.x86.fma.vfnmsub.pd.256")
},
"_rdrand16_step" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16, &::I32]; &PARTS }); &AGG },
definition: Named("llvm.x86.rdrand.16")
},
"_rdrand32_step" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32, &::I32]; &PARTS }); &AGG },
definition: Named("llvm.x86.rdrand.32")
},
"_rdrand64_step" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64, &::I32]; &PARTS }); &AGG },
definition: Named("llvm.x86.rdrand.64")
},
"_rdseed16_step" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16, &::I32]; &PARTS }); &AGG },
definition: Named("llvm.x86.rdseed.16")
},
"_rdseed32_step" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32, &::I32]; &PARTS }); &AGG },
definition: Named("llvm.x86.rdseed.32")
},
"_rdseed64_step" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS },
output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64, &::I32]; &PARTS }); &AGG },
definition: Named("llvm.x86.rdseed.64")
},
"_mm_adds_epi8" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
output: &::I8x16,