Rollup merge of #47964 - jcowgill:mips64-abi, r=eddyb
rustc_trans: rewrite mips64 ABI code This PR rewrites the ABI handling code for 64-bit MIPS and should fix various FFI issues including #47290. To accomodate the 64-bit ABI I have had to add a new `CastTarget` variant which I've called `Chunked` (though maybe this isn't the best name). This allows an ABI to cast to some arbitrary structure of `Reg` types. This is required on MIPS which might need to cast to a structure containing a mixture of `i64` and `f64` types.
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kennytm
GitHub
commit
f5116e712f
@ -40,7 +40,7 @@ use rustc::ty::layout::{self, Align, Size, TyLayout};
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use rustc::ty::layout::{HasDataLayout, LayoutOf};
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use libc::c_uint;
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use std::{cmp, iter};
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use std::cmp;
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pub use syntax::abi::Abi;
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pub use rustc::ty::layout::{FAT_PTR_ADDR, FAT_PTR_EXTRA};
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@ -279,30 +279,6 @@ impl Uniform {
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pub fn align(&self, cx: &CodegenCx) -> Align {
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self.unit.align(cx)
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}
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pub fn llvm_type(&self, cx: &CodegenCx) -> Type {
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let llunit = self.unit.llvm_type(cx);
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if self.total <= self.unit.size {
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return llunit;
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}
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let count = self.total.bytes() / self.unit.size.bytes();
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let rem_bytes = self.total.bytes() % self.unit.size.bytes();
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if rem_bytes == 0 {
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return Type::array(&llunit, count);
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}
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// Only integers can be really split further.
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assert_eq!(self.unit.kind, RegKind::Integer);
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let args: Vec<_> = (0..count).map(|_| llunit)
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.chain(iter::once(Type::ix(cx, rem_bytes * 8)))
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.collect();
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Type::struct_(cx, &args, false)
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}
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}
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pub trait LayoutExt<'tcx> {
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@ -405,55 +381,81 @@ impl<'tcx> LayoutExt<'tcx> for TyLayout<'tcx> {
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}
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum CastTarget {
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Uniform(Uniform),
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Pair(Reg, Reg)
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pub struct CastTarget {
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pub prefix: [Option<RegKind>; 8],
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pub prefix_chunk: Size,
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pub rest: Uniform,
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}
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impl From<Reg> for CastTarget {
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fn from(unit: Reg) -> CastTarget {
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CastTarget::Uniform(Uniform::from(unit))
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CastTarget::from(Uniform::from(unit))
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}
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}
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impl From<Uniform> for CastTarget {
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fn from(uniform: Uniform) -> CastTarget {
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CastTarget::Uniform(uniform)
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CastTarget {
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prefix: [None; 8],
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prefix_chunk: Size::from_bytes(0),
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rest: uniform
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}
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}
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}
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impl CastTarget {
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pub fn size(&self, cx: &CodegenCx) -> Size {
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match *self {
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CastTarget::Uniform(u) => u.total,
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CastTarget::Pair(a, b) => {
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(a.size.abi_align(a.align(cx)) + b.size)
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.abi_align(self.align(cx))
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}
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pub fn pair(a: Reg, b: Reg) -> CastTarget {
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CastTarget {
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prefix: [Some(a.kind), None, None, None, None, None, None, None],
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prefix_chunk: a.size,
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rest: Uniform::from(b)
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}
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}
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pub fn size(&self, cx: &CodegenCx) -> Size {
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(self.prefix_chunk * self.prefix.iter().filter(|x| x.is_some()).count() as u64)
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.abi_align(self.rest.align(cx)) + self.rest.total
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}
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pub fn align(&self, cx: &CodegenCx) -> Align {
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match *self {
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CastTarget::Uniform(u) => u.align(cx),
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CastTarget::Pair(a, b) => {
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cx.data_layout().aggregate_align
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.max(a.align(cx))
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.max(b.align(cx))
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}
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}
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self.prefix.iter()
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.filter_map(|x| x.map(|kind| Reg { kind: kind, size: self.prefix_chunk }.align(cx)))
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.fold(cx.data_layout().aggregate_align.max(self.rest.align(cx)),
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|acc, align| acc.max(align))
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}
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pub fn llvm_type(&self, cx: &CodegenCx) -> Type {
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match *self {
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CastTarget::Uniform(u) => u.llvm_type(cx),
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CastTarget::Pair(a, b) => {
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Type::struct_(cx, &[
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a.llvm_type(cx),
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b.llvm_type(cx)
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], false)
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let rest_ll_unit = self.rest.unit.llvm_type(cx);
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let rest_count = self.rest.total.bytes() / self.rest.unit.size.bytes();
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let rem_bytes = self.rest.total.bytes() % self.rest.unit.size.bytes();
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if self.prefix.iter().all(|x| x.is_none()) {
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// Simplify to a single unit when there is no prefix and size <= unit size
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if self.rest.total <= self.rest.unit.size {
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return rest_ll_unit;
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}
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// Simplify to array when all chunks are the same size and type
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if rem_bytes == 0 {
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return Type::array(&rest_ll_unit, rest_count);
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}
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}
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// Create list of fields in the main structure
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let mut args: Vec<_> =
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self.prefix.iter().flat_map(|option_kind| option_kind.map(
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|kind| Reg { kind: kind, size: self.prefix_chunk }.llvm_type(cx)))
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.chain((0..rest_count).map(|_| rest_ll_unit))
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.collect();
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// Append final integer
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if rem_bytes != 0 {
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// Only integers can be really split further.
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assert_eq!(self.rest.unit.kind, RegKind::Integer);
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args.push(Type::ix(cx, rem_bytes * 8));
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}
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Type::struct_(cx, &args, false)
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}
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}
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@ -8,50 +8,160 @@
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// option. This file may not be copied, modified, or distributed
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// except according to those terms.
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use abi::{ArgType, FnType, LayoutExt, Reg, Uniform};
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use abi::{ArgAttribute, ArgType, CastTarget, FnType, LayoutExt, PassMode, Reg, RegKind, Uniform};
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use context::CodegenCx;
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use rustc::ty::layout::{self, Size};
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use rustc::ty::layout::Size;
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fn extend_integer_width_mips(arg: &mut ArgType, bits: u64) {
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// Always sign extend u32 values on 64-bit mips
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if let layout::Abi::Scalar(ref scalar) = arg.layout.abi {
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if let layout::Int(i, signed) = scalar.value {
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if !signed && i.size().bits() == 32 {
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if let PassMode::Direct(ref mut attrs) = arg.mode {
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attrs.set(ArgAttribute::SExt);
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return;
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}
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}
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}
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}
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fn classify_ret_ty<'a, 'tcx>(cx: &CodegenCx<'a, 'tcx>,
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ret: &mut ArgType<'tcx>,
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offset: &mut Size) {
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if !ret.layout.is_aggregate() {
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ret.extend_integer_width_to(64);
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arg.extend_integer_width_to(bits);
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}
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fn bits_to_int_reg(bits: u64) -> Reg {
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if bits <= 8 {
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Reg::i8()
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} else if bits <= 16 {
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Reg::i16()
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} else if bits <= 32 {
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Reg::i32()
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} else {
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ret.make_indirect();
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*offset += cx.tcx.data_layout.pointer_size;
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Reg::i64()
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}
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}
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fn classify_arg_ty(cx: &CodegenCx, arg: &mut ArgType, offset: &mut Size) {
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let dl = &cx.tcx.data_layout;
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let size = arg.layout.size;
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let align = arg.layout.align.max(dl.i32_align).min(dl.i64_align);
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fn float_reg<'a, 'tcx>(cx: &CodegenCx<'a, 'tcx>, ret: &ArgType<'tcx>, i: usize) -> Option<Reg> {
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match ret.layout.field(cx, i).abi {
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layout::Abi::Scalar(ref scalar) => match scalar.value {
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layout::F32 => Some(Reg::f32()),
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layout::F64 => Some(Reg::f64()),
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_ => None
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},
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_ => None
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}
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}
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if arg.layout.is_aggregate() {
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arg.cast_to(Uniform {
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unit: Reg::i64(),
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total: size
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});
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if !offset.is_abi_aligned(align) {
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arg.pad_with(Reg::i64());
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}
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} else {
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arg.extend_integer_width_to(64);
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fn classify_ret_ty<'a, 'tcx>(cx: &CodegenCx<'a, 'tcx>, ret: &mut ArgType<'tcx>) {
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if !ret.layout.is_aggregate() {
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extend_integer_width_mips(ret, 64);
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return;
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}
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*offset = offset.abi_align(align) + size.abi_align(align);
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let size = ret.layout.size;
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let bits = size.bits();
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if bits <= 128 {
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// Unlike other architectures which return aggregates in registers, MIPS n64 limits the
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// use of float registers to structures (not unions) containing exactly one or two
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// float fields.
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if let layout::FieldPlacement::Arbitrary { .. } = ret.layout.fields {
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if ret.layout.fields.count() == 1 {
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if let Some(reg) = float_reg(cx, ret, 0) {
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ret.cast_to(reg);
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return;
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}
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} else if ret.layout.fields.count() == 2 {
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if let Some(reg0) = float_reg(cx, ret, 0) {
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if let Some(reg1) = float_reg(cx, ret, 1) {
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ret.cast_to(CastTarget::pair(reg0, reg1));
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return;
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}
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}
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}
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}
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// Cast to a uniform int structure
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ret.cast_to(Uniform {
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unit: bits_to_int_reg(bits),
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total: size
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});
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} else {
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ret.make_indirect();
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}
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}
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fn classify_arg_ty<'a, 'tcx>(cx: &CodegenCx<'a, 'tcx>, arg: &mut ArgType<'tcx>) {
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if !arg.layout.is_aggregate() {
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extend_integer_width_mips(arg, 64);
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return;
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}
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let dl = &cx.tcx.data_layout;
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let size = arg.layout.size;
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let mut prefix = [None; 8];
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let mut prefix_index = 0;
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match arg.layout.fields {
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layout::FieldPlacement::Array { .. } => {
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// Arrays are passed indirectly
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arg.make_indirect();
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return;
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}
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layout::FieldPlacement::Union(_) => {
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// Unions and are always treated as a series of 64-bit integer chunks
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},
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layout::FieldPlacement::Arbitrary { .. } => {
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// Structures are split up into a series of 64-bit integer chunks, but any aligned
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// doubles not part of another aggregate are passed as floats.
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let mut last_offset = Size::from_bytes(0);
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for i in 0..arg.layout.fields.count() {
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let field = arg.layout.field(cx, i);
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let offset = arg.layout.fields.offset(i);
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// We only care about aligned doubles
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if let layout::Abi::Scalar(ref scalar) = field.abi {
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if let layout::F64 = scalar.value {
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if offset.is_abi_aligned(dl.f64_align) {
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// Insert enough integers to cover [last_offset, offset)
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assert!(last_offset.is_abi_aligned(dl.f64_align));
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for _ in 0..((offset - last_offset).bits() / 64)
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.min((prefix.len() - prefix_index) as u64) {
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prefix[prefix_index] = Some(RegKind::Integer);
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prefix_index += 1;
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}
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if prefix_index == prefix.len() {
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break;
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}
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prefix[prefix_index] = Some(RegKind::Float);
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prefix_index += 1;
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last_offset = offset + Reg::f64().size;
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}
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}
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}
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}
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}
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};
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// Extract first 8 chunks as the prefix
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let rest_size = size - Size::from_bytes(8) * prefix_index as u64;
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arg.cast_to(CastTarget {
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prefix: prefix,
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prefix_chunk: Size::from_bytes(8),
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rest: Uniform { unit: Reg::i64(), total: rest_size }
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});
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}
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pub fn compute_abi_info<'a, 'tcx>(cx: &CodegenCx<'a, 'tcx>, fty: &mut FnType<'tcx>) {
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let mut offset = Size::from_bytes(0);
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if !fty.ret.is_ignore() {
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classify_ret_ty(cx, &mut fty.ret, &mut offset);
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classify_ret_ty(cx, &mut fty.ret);
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}
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for arg in &mut fty.args {
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if arg.is_ignore() { continue; }
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classify_arg_ty(cx, arg, &mut offset);
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classify_arg_ty(cx, arg);
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}
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}
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@ -171,7 +171,7 @@ fn cast_target(cls: &[Option<Class>], size: Size) -> CastTarget {
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let mut target = CastTarget::from(lo);
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if size > offset {
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if let Some(hi) = reg_component(cls, &mut i, size - offset) {
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target = CastTarget::Pair(lo, hi);
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target = CastTarget::pair(lo, hi);
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}
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}
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assert_eq!(reg_component(cls, &mut i, Size::from_bytes(0)), None);
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