399 lines
11 KiB
Rust
399 lines
11 KiB
Rust
// Copyright 2012-2013 The Rust Project Developers. See the COPYRIGHT
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// file at the top-level directory of this distribution and at
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// http://rust-lang.org/COPYRIGHT.
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//
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// Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
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// http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
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// <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
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// option. This file may not be copied, modified, or distributed
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// except according to those terms.
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// The classification code for the x86_64 ABI is taken from the clay language
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// https://github.com/jckarter/clay/blob/master/compiler/src/externals.cpp
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#![allow(non_upper_case_globals)]
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use self::RegClass::*;
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use llvm::{Integer, Pointer, Float, Double};
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use llvm::{Struct, Array, Vector};
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use abi::{self, ArgType, ArgAttribute, FnType};
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use context::CrateContext;
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use type_::Type;
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#[derive(Clone, Copy, PartialEq)]
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enum RegClass {
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NoClass,
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Int,
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SSEFs,
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SSEFv,
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SSEDs,
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SSEDv,
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SSEInt(/* bitwidth */ u64),
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/// Data that can appear in the upper half of an SSE register.
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SSEUp,
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X87,
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X87Up,
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ComplexX87,
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Memory
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}
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trait TypeMethods {
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fn is_reg_ty(&self) -> bool;
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}
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impl TypeMethods for Type {
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fn is_reg_ty(&self) -> bool {
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match self.kind() {
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Integer | Pointer | Float | Double => true,
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_ => false
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}
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}
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}
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impl RegClass {
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fn is_sse(&self) -> bool {
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match *self {
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SSEFs | SSEFv | SSEDs | SSEDv | SSEInt(_) => true,
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_ => false
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}
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}
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}
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trait ClassList {
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fn is_pass_byval(&self) -> bool;
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fn is_ret_bysret(&self) -> bool;
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}
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impl ClassList for [RegClass] {
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fn is_pass_byval(&self) -> bool {
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if self.is_empty() { return false; }
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let class = self[0];
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class == Memory
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|| class == X87
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|| class == ComplexX87
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}
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fn is_ret_bysret(&self) -> bool {
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if self.is_empty() { return false; }
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self[0] == Memory
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}
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}
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fn classify_ty(ty: Type) -> Vec<RegClass> {
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fn align(off: usize, ty: Type) -> usize {
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let a = ty_align(ty);
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return (off + a - 1) / a * a;
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}
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fn ty_align(ty: Type) -> usize {
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abi::ty_align(ty, 8)
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}
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fn ty_size(ty: Type) -> usize {
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abi::ty_size(ty, 8)
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}
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fn all_mem(cls: &mut [RegClass]) {
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for elt in cls {
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*elt = Memory;
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}
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}
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fn unify(cls: &mut [RegClass],
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i: usize,
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newv: RegClass) {
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if cls[i] == newv { return }
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let to_write = match (cls[i], newv) {
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(NoClass, _) => newv,
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(_, NoClass) => return,
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(Memory, _) |
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(_, Memory) => Memory,
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(Int, _) |
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(_, Int) => Int,
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(X87, _) |
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(X87Up, _) |
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(ComplexX87, _) |
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(_, X87) |
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(_, X87Up) |
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(_, ComplexX87) => Memory,
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(SSEFv, SSEUp) |
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(SSEFs, SSEUp) |
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(SSEDv, SSEUp) |
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(SSEDs, SSEUp) |
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(SSEInt(_), SSEUp) => return,
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(..) => newv
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};
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cls[i] = to_write;
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}
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fn classify_struct(tys: &[Type],
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cls: &mut [RegClass],
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i: usize,
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off: usize,
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packed: bool) {
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let mut field_off = off;
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for ty in tys {
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if !packed {
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field_off = align(field_off, *ty);
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}
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classify(*ty, cls, i, field_off);
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field_off += ty_size(*ty);
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}
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}
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fn classify(ty: Type,
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cls: &mut [RegClass], ix: usize,
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off: usize) {
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let t_align = ty_align(ty);
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let t_size = ty_size(ty);
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let misalign = off % t_align;
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if misalign != 0 {
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let mut i = off / 8;
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let e = (off + t_size + 7) / 8;
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while i < e {
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unify(cls, ix + i, Memory);
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i += 1;
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}
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return;
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}
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match ty.kind() {
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Integer |
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Pointer => {
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unify(cls, ix + off / 8, Int);
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}
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Float => {
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if off % 8 == 4 {
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unify(cls, ix + off / 8, SSEFv);
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} else {
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unify(cls, ix + off / 8, SSEFs);
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}
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}
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Double => {
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unify(cls, ix + off / 8, SSEDs);
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}
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Struct => {
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classify_struct(&ty.field_types(), cls, ix, off, ty.is_packed());
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}
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Array => {
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let len = ty.array_length();
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let elt = ty.element_type();
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let eltsz = ty_size(elt);
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let mut i = 0;
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while i < len {
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classify(elt, cls, ix, off + i * eltsz);
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i += 1;
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}
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}
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Vector => {
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let len = ty.vector_length();
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let elt = ty.element_type();
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let eltsz = ty_size(elt);
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let mut reg = match elt.kind() {
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Integer => SSEInt(elt.int_width()),
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Float => SSEFv,
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Double => SSEDv,
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_ => bug!("classify: unhandled vector element type")
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};
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let mut i = 0;
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while i < len {
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unify(cls, ix + (off + i * eltsz) / 8, reg);
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// everything after the first one is the upper
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// half of a register.
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reg = SSEUp;
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i += 1;
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}
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}
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_ => bug!("classify: unhandled type")
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}
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}
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fn fixup(ty: Type, cls: &mut [RegClass]) {
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let mut i = 0;
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let ty_kind = ty.kind();
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let e = cls.len();
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if cls.len() > 2 && (ty_kind == Struct || ty_kind == Array || ty_kind == Vector) {
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if cls[i].is_sse() {
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i += 1;
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while i < e {
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if cls[i] != SSEUp {
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all_mem(cls);
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return;
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}
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i += 1;
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}
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} else {
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all_mem(cls);
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return
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}
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} else {
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while i < e {
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if cls[i] == Memory {
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all_mem(cls);
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return;
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}
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if cls[i] == X87Up {
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// for darwin
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// cls[i] = SSEDs;
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all_mem(cls);
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return;
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}
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if cls[i] == SSEUp {
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cls[i] = SSEDv;
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} else if cls[i].is_sse() {
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i += 1;
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while i != e && cls[i] == SSEUp { i += 1; }
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} else if cls[i] == X87 {
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i += 1;
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while i != e && cls[i] == X87Up { i += 1; }
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} else {
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i += 1;
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}
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}
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}
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}
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let words = (ty_size(ty) + 7) / 8;
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let mut cls = vec![NoClass; words];
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if words > 4 {
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all_mem(&mut cls);
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return cls;
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}
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classify(ty, &mut cls, 0, 0);
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fixup(ty, &mut cls);
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return cls;
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}
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fn llreg_ty(ccx: &CrateContext, cls: &[RegClass]) -> Type {
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fn llvec_len(cls: &[RegClass]) -> usize {
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let mut len = 1;
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for c in cls {
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if *c != SSEUp {
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break;
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}
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len += 1;
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}
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return len;
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}
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let mut tys = Vec::new();
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let mut i = 0;
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let e = cls.len();
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while i < e {
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match cls[i] {
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Int => {
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tys.push(Type::i64(ccx));
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}
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SSEFv | SSEDv | SSEInt(_) => {
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let (elts_per_word, elt_ty) = match cls[i] {
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SSEFv => (2, Type::f32(ccx)),
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SSEDv => (1, Type::f64(ccx)),
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SSEInt(bits) => {
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assert!(bits == 8 || bits == 16 || bits == 32 || bits == 64,
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"llreg_ty: unsupported SSEInt width {}", bits);
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(64 / bits, Type::ix(ccx, bits))
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}
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_ => bug!(),
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};
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let vec_len = llvec_len(&cls[i + 1..]);
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let vec_ty = Type::vector(&elt_ty, vec_len as u64 * elts_per_word);
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tys.push(vec_ty);
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i += vec_len;
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continue;
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}
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SSEFs => {
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tys.push(Type::f32(ccx));
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}
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SSEDs => {
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tys.push(Type::f64(ccx));
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}
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_ => bug!("llregtype: unhandled class")
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}
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i += 1;
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}
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if tys.len() == 1 && tys[0].kind() == Vector {
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// if the type contains only a vector, pass it as that vector.
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tys[0]
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} else {
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Type::struct_(ccx, &tys, false)
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}
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}
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pub fn compute_abi_info(ccx: &CrateContext, fty: &mut FnType) {
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fn x86_64_ty<F>(ccx: &CrateContext,
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arg: &mut ArgType,
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is_mem_cls: F,
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ind_attr: Option<ArgAttribute>)
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where F: FnOnce(&[RegClass]) -> bool
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{
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if !arg.ty.is_reg_ty() {
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let cls = classify_ty(arg.ty);
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if is_mem_cls(&cls) {
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arg.make_indirect(ccx);
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if let Some(attr) = ind_attr {
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arg.attrs.set(attr);
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}
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} else {
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arg.cast = Some(llreg_ty(ccx, &cls));
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}
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} else {
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arg.extend_integer_width_to(32);
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}
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}
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let mut int_regs = 6; // RDI, RSI, RDX, RCX, R8, R9
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let mut sse_regs = 8; // XMM0-7
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if !fty.ret.is_ignore() {
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x86_64_ty(ccx, &mut fty.ret, |cls| {
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if cls.is_ret_bysret() {
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// `sret` parameter thus one less register available
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int_regs -= 1;
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true
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} else {
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false
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}
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}, None);
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}
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for arg in &mut fty.args {
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if arg.is_ignore() { continue; }
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x86_64_ty(ccx, arg, |cls| {
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let needed_int = cls.iter().filter(|&&c| c == Int).count() as isize;
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let needed_sse = cls.iter().filter(|c| c.is_sse()).count() as isize;
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let in_mem = cls.is_pass_byval() ||
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int_regs < needed_int ||
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sse_regs < needed_sse;
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if in_mem {
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// `byval` parameter thus one less integer register available
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int_regs -= 1;
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} else {
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// split into sized chunks passed individually
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int_regs -= needed_int;
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sse_regs -= needed_sse;
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}
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in_mem
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}, Some(ArgAttribute::ByVal));
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// An integer, pointer, double or float parameter
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// thus the above closure passed to `x86_64_ty` won't
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// get called.
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match arg.ty.kind() {
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Integer | Pointer => int_regs -= 1,
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Double | Float => sse_regs -= 1,
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_ => {}
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}
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}
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}
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