mirror of https://github.com/NekoX-Dev/NekoX.git
341 lines
16 KiB
C
341 lines
16 KiB
C
/*!
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* \copy
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* Copyright (c) 2013, Loongson Technology Co.,Ltd.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef ASMDEFS_MMI_H_
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#define ASMDEFS_MMI_H_
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#define CACHE_LINE_SIZE 32
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#if defined(_ABI64) && _MIPS_SIM == _ABI64
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# define mips_reg int64_t
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# define PTRSIZE " 8 "
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# define PTRLOG " 3 "
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# define PTR_ADDU "daddu "
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# define PTR_ADDIU "daddiu "
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# define PTR_ADDI "daddi "
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# define PTR_SUBU "dsubu "
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# define PTR_L "ld "
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# define PTR_S "sd "
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# define PTR_SRA "dsra "
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# define PTR_SRL "dsrl "
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# define PTR_SLL "dsll "
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#else
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# define mips_reg int32_t
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# define PTRSIZE " 4 "
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# define PTRLOG " 2 "
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# define PTR_ADDU "addu "
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# define PTR_ADDIU "addiu "
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# define PTR_ADDI "addi "
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# define PTR_SUBU "subu "
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# define PTR_L "lw "
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# define PTR_S "sw "
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# define PTR_SRA "sra "
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# define PTR_SRL "srl "
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# define PTR_SLL "sll "
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#endif
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#define MMI_XSawp_BH(f0, f2, f4, f6, f8, f10) \
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"mov.d "#f8", "#f2" \n\t" \
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"punpckhbh "#f2", "#f0", "#f4" \n\t" \
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"punpcklbh "#f0", "#f0", "#f4" \n\t" \
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"punpckhbh "#f10", "#f8", "#f6" \n\t" \
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"punpcklbh "#f8", "#f8", "#f6" \n\t"
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#define MMI_XSawp_HW(f0, f2, f4, f6, f8, f10) \
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"mov.d "#f8", "#f2" \n\t" \
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"punpckhhw "#f2", "#f0", "#f4" \n\t" \
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"punpcklhw "#f0", "#f0", "#f4" \n\t" \
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"punpckhhw "#f10", "#f8", "#f6" \n\t" \
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"punpcklhw "#f8", "#f8", "#f6" \n\t"
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#define MMI_XSawp_WD(f0, f2, f4, f6, f8, f10) \
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"mov.d "#f8", "#f2" \n\t" \
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"punpckhwd "#f2", "#f0", "#f4" \n\t" \
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"punpcklwd "#f0", "#f0", "#f4" \n\t" \
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"punpckhwd "#f10", "#f8", "#f6" \n\t" \
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"punpcklwd "#f8", "#f8", "#f6" \n\t"
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#define MMI_XSawp_DQ(f0, f2, f4, f6, f8, f10) \
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"mov.d "#f8", "#f2" \n\t" \
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"mov.d "#f2", "#f4" \n\t" \
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"mov.d "#f10", "#f6" \n\t"
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#define WELS_AbsH(f0, f2, f4, f6, f8, f10) \
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"xor "#f8", "#f8", "#f8" \n\t" \
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"psubh "#f10", "#f8", "#f6" \n\t" \
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"psubh "#f8", "#f8", "#f4" \n\t" \
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"pmaxsh "#f0", "#f4", "#f8" \n\t" \
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"pmaxsh "#f2", "#f6", "#f10" \n\t"
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#define MMI_SumSub(f0, f2, f4, f6, f8, f10) \
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"mov.d "#f8", "#f4" \n\t" \
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"mov.d "#f10", "#f6" \n\t" \
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"paddh "#f4", "#f4", "#f0" \n\t" \
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"paddh "#f6", "#f6", "#f2" \n\t" \
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"psubh "#f0", "#f0", "#f8" \n\t" \
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"psubh "#f2", "#f2", "#f10" \n\t"
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#define MMI_LoadDiff8P(f0, f2, f4, f6, f8, r0, r1) \
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"gsldlc1 "#f0", 0x7("#r0") \n\t" \
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"gsldlc1 "#f4", 0x7("#r1") \n\t" \
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"gsldrc1 "#f0", 0x0("#r0") \n\t" \
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"gsldrc1 "#f4", 0x0("#r1") \n\t" \
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"punpckhbh "#f2", "#f0", "#f8" \n\t" \
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"punpcklbh "#f0", "#f0", "#f8" \n\t" \
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"punpckhbh "#f6", "#f4", "#f8" \n\t" \
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"punpcklbh "#f4", "#f4", "#f8" \n\t" \
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"psubh "#f0", "#f0", "#f4" \n\t" \
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"psubh "#f2", "#f2", "#f6" \n\t"
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#define MMI_TransTwo4x4H(f0, f2, f4, f6, f8, f10, f12, f14, f16, f18) \
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MMI_XSawp_HW(f0, f2, f4, f6, f16, f18) \
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MMI_XSawp_HW(f8, f10, f12, f14, f4, f6) \
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MMI_XSawp_WD(f0, f2, f8, f10, f12, f14) \
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MMI_XSawp_WD(f16, f18, f4, f6, f8, f10) \
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MMI_XSawp_DQ(f0, f2, f16, f18, f4, f6) \
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MMI_XSawp_DQ(f12, f14, f8, f10, f16, f18)
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#define MMI_TransTwo8x8B(f0, f2, f4, f6, f8, f10, f12, f14, f16, f18, f20, f22, f24, f26, f28, f30, r0, r1) \
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"dmfc1 "#r0", "#f28" \n\t" \
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"dmfc1 "#r1", "#f30" \n\t" \
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MMI_XSawp_BH(f0, f2, f4, f6, f28, f30) \
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MMI_XSawp_BH(f8, f10, f12, f14, f4, f6) \
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MMI_XSawp_BH(f16, f18, f20, f22, f12, f14) \
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"dmtc1 "#r0", "#f20" \n\t" \
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"dmtc1 "#r1", "#f22" \n\t" \
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"dmfc1 "#r0", "#f12" \n\t" \
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"dmfc1 "#r1", "#f14" \n\t" \
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MMI_XSawp_BH(f24, f26, f20, f22, f12, f14) \
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MMI_XSawp_HW(f0, f2, f8, f10, f20, f22) \
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MMI_XSawp_HW(f28, f30, f4, f6, f8, f10) \
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MMI_XSawp_HW(f16, f18, f24, f26, f4, f6) \
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"dmtc1 "#r0", "#f24" \n\t" \
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"dmtc1 "#r1", "#f26" \n\t" \
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"dmfc1 "#r0", "#f8" \n\t" \
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"dmfc1 "#r1", "#f10" \n\t" \
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MMI_XSawp_HW(f24, f26, f12, f14, f8, f10) \
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MMI_XSawp_WD(f0, f2, f16, f18, f12, f14) \
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MMI_XSawp_WD(f20, f22, f4, f6, f16, f18) \
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MMI_XSawp_WD(f28, f30, f24, f26, f4, f6) \
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"dmtc1 "#r0", "#f24" \n\t" \
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"dmtc1 "#r1", "#f26" \n\t" \
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"dmfc1 "#r0", "#f16" \n\t" \
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"dmfc1 "#r1", "#f18" \n\t" \
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MMI_XSawp_WD(f24, f26, f8, f10, f16, f18) \
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MMI_XSawp_DQ(f0, f2, f28, f30, f8, f10) \
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MMI_XSawp_DQ(f12, f14, f4, f6, f28, f30) \
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MMI_XSawp_DQ(f20, f22, f24, f26, f4, f6) \
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"dmtc1 "#r0", "#f24" \n\t" \
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"dmtc1 "#r1", "#f26" \n\t" \
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"dmfc1 "#r0", "#f0" \n\t" \
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"dmfc1 "#r1", "#f2" \n\t" \
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MMI_XSawp_DQ(f24, f26, f16, f18, f0, f2) \
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"dmtc1 "#r0", "#f16" \n\t" \
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"dmtc1 "#r1", "#f18" \n\t"
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#define MMI_XSwap_HW_SINGLE(f0, f2, f4) \
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"punpckhhw "#f4", "#f0", "#f2" \n\t" \
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"punpcklhw "#f0", "#f0", "#f2" \n\t"
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#define MMI_XSwap_WD_SINGLE(f0, f2, f4) \
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"punpckhwd "#f4", "#f0", "#f2" \n\t" \
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"punpcklwd "#f0", "#f0", "#f2" \n\t"
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#define MMI_Trans4x4H_SINGLE(f0, f2, f4, f6, f8) \
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MMI_XSwap_HW_SINGLE(f0, f2, f8) \
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MMI_XSwap_HW_SINGLE(f4, f6, f2) \
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MMI_XSwap_WD_SINGLE(f0, f4, f6) \
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MMI_XSwap_WD_SINGLE(f8, f2, f4)
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#define MMI_SumSub_SINGLE(f0, f2, f4) \
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"mov.d "#f4", "#f2" \n\t" \
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"psubh "#f2", "#f2", "#f0" \n\t" \
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"paddh "#f0", "#f0", "#f4" \n\t"
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#define MMI_SumSubMul2_SINGLE(f0, f2, f4, f6) \
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"mov.d "#f4", "#f0" \n\t" \
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"psllh "#f0", "#f0", "#f6" \n\t" \
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"paddh "#f0", "#f0", "#f2" \n\t" \
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"psllh "#f2", "#f2", "#f6" \n\t" \
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"psubh "#f4", "#f4", "#f2" \n\t"
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//f4 should be 0x0
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#define MMI_Copy8Times(f0, f2, f4, r0) \
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"dmtc1 "#r0", "#f0" \n\t" \
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"pshufh "#f0", "#f0", "#f4" \n\t" \
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"mov.d "#f2", "#f0" \n\t"
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//f4 should be 0x0
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#define MMI_Copy16Times(f0, f2, f4, r0) \
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"dmtc1 "#r0", "#f0" \n\t" \
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"punpcklbh "#f0", "#f0", "#f0" \n\t" \
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"pshufh "#f0", "#f0", "#f4" \n\t" \
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"mov.d "#f2", "#f0" \n\t"
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#define MMI_SumSubDiv2_SINGLE(f0, f2, f4, f6) \
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"psrah "#f4", "#f2", "#f6" \n\t" \
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"paddh "#f4", "#f4", "#f0" \n\t" \
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"psrah "#f0", "#f0", "#f6" \n\t" \
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"psubh "#f0", "#f0", "#f2" \n\t"
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#define MMI_IDCT_SINGLE(f0, f2, f4, f6, f8, f10, f12) \
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MMI_SumSub_SINGLE(f6, f8, f10) \
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MMI_SumSubDiv2_SINGLE(f4, f2, f0, f12) \
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MMI_SumSub_SINGLE(f0, f6, f10) \
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MMI_SumSub_SINGLE(f4, f8, f10)
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#define MMI_StoreDiff4P_SINGLE(f0, f2, f4, f6, r0, r1, f8) \
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"gsldlc1 "#f2", 0x7("#r1") \n\t" \
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"gsldrc1 "#f2", 0x0("#r1") \n\t" \
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"punpcklbh "#f2", "#f2", "#f6" \n\t" \
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"paddh "#f0", "#f0", "#f4" \n\t" \
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"psrah "#f0", "#f0", "#f8" \n\t" \
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"paddsh "#f0", "#f0", "#f2" \n\t" \
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"packushb "#f0", "#f0", "#f2" \n\t" \
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"gsswlc1 "#f0", 0x3("#r0") \n\t" \
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"gsswrc1 "#f0", 0x0("#r0") \n\t"
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#define SUMH_HORIZON(f0, f2, f4, f6, f8) \
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"paddh "#f0", "#f0", "#f2" \n\t" \
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"punpckhhw "#f2", "#f0", "#f8" \n\t" \
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"punpcklhw "#f0", "#f0", "#f8" \n\t" \
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"paddw "#f0", "#f0", "#f2" \n\t" \
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"punpckhwd "#f2", "#f0", "#f0" \n\t" \
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"paddw "#f0", "#f0", "#f2" \n\t"
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#define LOAD_COLUMN(f0, f2, f4, f6, f8, f10, f12, f14, r0, r1, r2) \
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"daddu "#r2", "#r0", "#r1" \n\t" \
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"gsldlc1 "#f0", 0x7("#r0") \n\t" \
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"gsldlc1 "#f4", 0x7("#r2") \n\t" \
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"gsldrc1 "#f0", 0x0("#r0") \n\t" \
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"gsldrc1 "#f4", 0x0("#r2") \n\t" \
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"punpcklbh "#f0", "#f0", "#f4" \n\t" \
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"daddu "#r0", "#r2", "#r1" \n\t" \
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"daddu "#r2", "#r0", "#r1" \n\t" \
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"gsldlc1 "#f8", 0x7("#r0") \n\t" \
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"gsldlc1 "#f4", 0x7("#r2") \n\t" \
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"gsldrc1 "#f8", 0x0("#r0") \n\t" \
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"gsldrc1 "#f4", 0x0("#r2") \n\t" \
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"punpcklbh "#f8", "#f8", "#f4" \n\t" \
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"punpckhhw "#f2", "#f0", "#f8" \n\t" \
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"punpcklhw "#f0", "#f0", "#f8" \n\t" \
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"daddu "#r0", "#r2", "#r1" \n\t" \
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"daddu "#r2", "#r0", "#r1" \n\t" \
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"gsldlc1 "#f12", 0x7("#r0") \n\t" \
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"gsldlc1 "#f4", 0x7("#r2") \n\t" \
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"gsldrc1 "#f12", 0x0("#r0") \n\t" \
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"gsldrc1 "#f4", 0x0("#r2") \n\t" \
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"punpcklbh "#f12", "#f12", "#f4" \n\t" \
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"daddu "#r0", "#r2", "#r1" \n\t" \
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"daddu "#r2", "#r0", "#r1" \n\t" \
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"gsldlc1 "#f8", 0x7("#r0") \n\t" \
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"gsldlc1 "#f4", 0x7("#r2") \n\t" \
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"gsldrc1 "#f8", 0x0("#r0") \n\t" \
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"gsldrc1 "#f4", 0x0("#r2") \n\t" \
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"punpcklbh "#f8", "#f8", "#f4" \n\t" \
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"punpckhhw "#f14", "#f12", "#f8" \n\t" \
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"punpcklhw "#f12", "#f12", "#f8" \n\t" \
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"daddu "#r0", "#r2", "#r1" \n\t" \
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"punpcklwd "#f0", "#f2", "#f14" \n\t" \
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"punpckhwd "#f2", "#f2", "#f14" \n\t"
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#define LOAD_COLUMN_C(f0, f2, f4, f6, r0, r1, r2) \
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"daddu "#r2", "#r0", "#r1" \n\t" \
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"gsldlc1 "#f0", 0x7("#r0") \n\t" \
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"gsldlc1 "#f2", 0x7("#r2") \n\t" \
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"gsldrc1 "#f0", 0x0("#r0") \n\t" \
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"gsldrc1 "#f2", 0x0("#r2") \n\t" \
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"punpcklbh "#f0", "#f0", "#f2" \n\t" \
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"daddu "#r0", "#r2", "#r1" \n\t" \
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"daddu "#r2", "#r0", "#r1" \n\t" \
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"gsldlc1 "#f4", 0x7("#r0") \n\t" \
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"gsldlc1 "#f2", 0x7("#r2") \n\t" \
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"gsldrc1 "#f4", 0x0("#r0") \n\t" \
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"gsldrc1 "#f2", 0x0("#r2") \n\t" \
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"punpcklbh "#f4", "#f4", "#f2" \n\t" \
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"punpckhhw "#f0", "#f0", "#f4" \n\t" \
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"daddu "#r0", "#r2", "#r1" \n\t"
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/**
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* backup register
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*/
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#define BACKUP_REG \
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double __attribute__((aligned(16))) __back_temp[8]; \
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if (_MIPS_SIM == _ABI64) \
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__asm__ volatile ( \
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"gssqc1 $f25, $f24, 0x00(%[temp]) \n\t" \
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"gssqc1 $f27, $f26, 0x10(%[temp]) \n\t" \
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"gssqc1 $f29, $f28, 0x20(%[temp]) \n\t" \
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"gssqc1 $f31, $f30, 0x30(%[temp]) \n\t" \
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: \
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: [temp]"r"(__back_temp) \
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: "memory" \
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); \
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else \
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__asm__ volatile ( \
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"gssqc1 $f22, $f20, 0x00(%[temp]) \n\t" \
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"gssqc1 $f26, $f24, 0x10(%[temp]) \n\t" \
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"gssqc1 $f30, $f28, 0x20(%[temp]) \n\t" \
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: \
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: [temp]"r"(__back_temp) \
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: "memory" \
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);
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/**
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* recover register
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*/
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#define RECOVER_REG \
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if (_MIPS_SIM == _ABI64) \
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__asm__ volatile ( \
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"gslqc1 $f25, $f24, 0x00(%[temp]) \n\t" \
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"gslqc1 $f27, $f26, 0x10(%[temp]) \n\t" \
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"gslqc1 $f29, $f28, 0x20(%[temp]) \n\t" \
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"gslqc1 $f31, $f30, 0x30(%[temp]) \n\t" \
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: \
|
|
: [temp]"r"(__back_temp) \
|
|
: "memory" \
|
|
); \
|
|
else \
|
|
__asm__ volatile ( \
|
|
"gslqc1 $f22, $f20, 0x00(%[temp]) \n\t" \
|
|
"gslqc1 $f26, $f24, 0x10(%[temp]) \n\t" \
|
|
"gslqc1 $f30, $f28, 0x20(%[temp]) \n\t" \
|
|
: \
|
|
: [temp]"r"(__back_temp) \
|
|
: "memory" \
|
|
);
|
|
|
|
# define OK 1
|
|
# define NOTOK 0
|
|
|
|
#endif /* ASMDEFS_MMI_H_ */
|