mirror of https://github.com/NekoX-Dev/NekoX.git
412 lines
10 KiB
NASM
412 lines
10 KiB
NASM
;*!
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;* \copy
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;* Copyright (c) 2010-2013, Cisco Systems
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;* All rights reserved.
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;*
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;* Redistribution and use in source and binary forms, with or without
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;* modification, are permitted provided that the following conditions
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;* are met:
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;*
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;* * Redistributions of source code must retain the above copyright
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;* notice, this list of conditions and the following disclaimer.
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;*
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;* * Redistributions in binary form must reproduce the above copyright
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;* notice, this list of conditions and the following disclaimer in
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;* the documentation and/or other materials provided with the
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;* distribution.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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;* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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;* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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;* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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;* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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;* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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;* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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;* POSSIBILITY OF SUCH DAMAGE.
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;*
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;*
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;* vaa.asm
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;*
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;* Abstract
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;* sse2 for pVaa routines
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;*
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;* History
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;* 04/14/2010 Created
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;* 06/07/2010 Added AnalysisVaaInfoIntra_sse2(ssse3)
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;* 06/10/2010 Tune rc_sad_frame_sse2 and got about 40% improvement
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;* 08/11/2010 Added abs_difference_mbrow_sse2 & sum_sqrsum_mbrow_sse2
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;*
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;*************************************************************************/
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%include "asm_inc.asm"
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;***********************************************************************
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; Macros and other preprocessor constants
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;***********************************************************************
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; by comparing it outperforms than phaddw(SSSE3) sets
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%macro SUM_WORD_8x2_SSE2 2 ; dst(pSrc), tmp
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; @sum_8x2 begin
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pshufd %2, %1, 04Eh ; 01001110 B
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paddw %1, %2
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pshuflw %2, %1, 04Eh ; 01001110 B
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paddw %1, %2
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pshuflw %2, %1, 0B1h ; 10110001 B
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paddw %1, %2
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; end of @sum_8x2
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%endmacro ; END of SUM_WORD_8x2_SSE2
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%macro VAA_AVG_BLOCK_SSE2 6 ; dst, t0, t1, t2, t3, t4
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movdqa %1, [r0 ] ; line 0
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movdqa %2, [r0+r1] ; line 1
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movdqa %3, %1
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punpcklbw %1, xmm7
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punpckhbw %3, xmm7
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movdqa %4, %2
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punpcklbw %4, xmm7
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punpckhbw %2, xmm7
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paddw %1, %4
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paddw %2, %3
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movdqa %3, [r0+r2] ; line 2
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movdqa %4, [r0+r3] ; line 3
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movdqa %5, %3
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punpcklbw %3, xmm7
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punpckhbw %5, xmm7
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movdqa %6, %4
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punpcklbw %6, xmm7
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punpckhbw %4, xmm7
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paddw %3, %6
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paddw %4, %5
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paddw %1, %3 ; block 0, 1
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paddw %2, %4 ; block 2, 3
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pshufd %3, %1, 0B1h
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pshufd %4, %2, 0B1h
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paddw %1, %3
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paddw %2, %4
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movdqa %3, %1
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movdqa %4, %2
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pshuflw %5, %1, 0B1h
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pshufhw %6, %3, 0B1h
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paddw %1, %5
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paddw %3, %6
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pshuflw %5, %2, 0B1h
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pshufhw %6, %4, 0B1h
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paddw %2, %5
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paddw %4, %6
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punpcklwd %1, %2
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punpckhwd %3, %4
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punpcklwd %1, %3
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psraw %1, $04
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%endmacro
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%macro VAA_AVG_BLOCK_SSSE3 6 ; dst, t0, t1, t2, t3, t4
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movdqa %1, [r0 ] ; line 0
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movdqa %2, [r0+r1] ; line 1
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movdqa %3, %1
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punpcklbw %1, xmm7
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punpckhbw %3, xmm7
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movdqa %4, %2
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punpcklbw %4, xmm7
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punpckhbw %2, xmm7
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paddw %1, %4
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paddw %2, %3
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movdqa %3, [r0+r2] ; line 2
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movdqa %4, [r0+r3] ; line 3
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movdqa %5, %3
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punpcklbw %3, xmm7
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punpckhbw %5, xmm7
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movdqa %6, %4
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punpcklbw %6, xmm7
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punpckhbw %4, xmm7
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paddw %3, %6
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paddw %4, %5
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paddw %1, %3 ; block 0, 1
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paddw %2, %4 ; block 2, 3
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phaddw %1, %2 ; block[0]: 0-15, 16-31; block[1]: 32-47, 48-63; ..
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phaddw %1, xmm7 ; block[0]: 0-15; block[1]: 16-31; block[2]: 32-47; block[3]: 48-63; ....
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psraw %1, $04
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%endmacro
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;***********************************************************************
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; Code
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;***********************************************************************
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SECTION .text
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; , 6/7/2010
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;***********************************************************************
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; int32_t AnalysisVaaInfoIntra_sse2( uint8_t *pDataY, const int32_t iLineSize );
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;***********************************************************************
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WELS_EXTERN AnalysisVaaInfoIntra_sse2
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%assign push_num 0
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LOAD_2_PARA
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PUSH_XMM 8
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SIGN_EXTENSION r1,r1d
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%ifdef X86_32
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push r3
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push r4
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push r5
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push r6
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%assign push_num push_num+4
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%endif
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mov r5,r7
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and r5,0fh
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sub r7,r5
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sub r7,32
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mov r2,r1
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sal r2,$01 ;r2 = 2*iLineSize
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mov r3,r2
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add r3,r1 ;r3 = 3*iLineSize
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mov r4,r2
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sal r4,$01 ;r4 = 4*iLineSize
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pxor xmm7, xmm7
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; loops
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VAA_AVG_BLOCK_SSE2 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5
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movq [r7], xmm0
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lea r0, [r0+r4]
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VAA_AVG_BLOCK_SSE2 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5
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movq [r7+8], xmm0
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lea r0, [r0+r4]
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VAA_AVG_BLOCK_SSE2 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5
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movq [r7+16], xmm0
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lea r0, [r0+r4]
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VAA_AVG_BLOCK_SSE2 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5
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movq [r7+24], xmm0
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movdqa xmm0, [r7] ; block 0~7
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movdqa xmm1, [r7+16] ; block 8~15
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movdqa xmm2, xmm0
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paddw xmm0, xmm1
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SUM_WORD_8x2_SSE2 xmm0, xmm3
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pmullw xmm1, xmm1
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pmullw xmm2, xmm2
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movdqa xmm3, xmm1
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movdqa xmm4, xmm2
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punpcklwd xmm1, xmm7
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punpckhwd xmm3, xmm7
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punpcklwd xmm2, xmm7
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punpckhwd xmm4, xmm7
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paddd xmm1, xmm2
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paddd xmm3, xmm4
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paddd xmm1, xmm3
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pshufd xmm2, xmm1, 01Bh
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paddd xmm1, xmm2
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pshufd xmm2, xmm1, 0B1h
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paddd xmm1, xmm2
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movd r2d, xmm0
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and r2, 0ffffh ; effective low work truncated
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mov r3, r2
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imul r2, r3
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sar r2, $04
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movd retrd, xmm1
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sub retrd, r2d
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add r7,32
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add r7,r5
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%ifdef X86_32
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pop r6
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pop r5
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pop r4
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pop r3
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%endif
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POP_XMM
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ret
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;***********************************************************************
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; int32_t AnalysisVaaInfoIntra_ssse3( uint8_t *pDataY, const int32_t iLineSize );
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;***********************************************************************
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WELS_EXTERN AnalysisVaaInfoIntra_ssse3
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%assign push_num 0
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LOAD_2_PARA
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PUSH_XMM 8
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SIGN_EXTENSION r1,r1d
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%ifdef X86_32
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push r3
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push r4
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push r5
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push r6
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%assign push_num push_num+4
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%endif
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mov r5,r7
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and r5,0fh
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sub r7,r5
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sub r7,32
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mov r2,r1
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sal r2,$01 ;r2 = 2*iLineSize
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mov r3,r2
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add r3,r1 ;r3 = 3*iLineSize
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mov r4,r2
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sal r4,$01 ;r4 = 4*iLineSize
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pxor xmm7, xmm7
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; loops
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VAA_AVG_BLOCK_SSSE3 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5
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movq [r7],xmm0
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lea r0,[r0+r4]
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VAA_AVG_BLOCK_SSSE3 xmm1, xmm2, xmm3, xmm4, xmm5, xmm6
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movq [r7+8],xmm1
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lea r0,[r0+r4]
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VAA_AVG_BLOCK_SSSE3 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5
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movq [r7+16],xmm0
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lea r0,[r0+r4]
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VAA_AVG_BLOCK_SSSE3 xmm1, xmm2, xmm3, xmm4, xmm5, xmm6
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movq [r7+24],xmm1
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movdqa xmm0,[r7]
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movdqa xmm1,[r7+16]
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movdqa xmm2, xmm0
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paddw xmm0, xmm1
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SUM_WORD_8x2_SSE2 xmm0, xmm3 ; better performance than that of phaddw sets
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pmullw xmm1, xmm1
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pmullw xmm2, xmm2
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movdqa xmm3, xmm1
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movdqa xmm4, xmm2
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punpcklwd xmm1, xmm7
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punpckhwd xmm3, xmm7
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punpcklwd xmm2, xmm7
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punpckhwd xmm4, xmm7
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paddd xmm1, xmm2
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paddd xmm3, xmm4
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paddd xmm1, xmm3
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pshufd xmm2, xmm1, 01Bh
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paddd xmm1, xmm2
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pshufd xmm2, xmm1, 0B1h
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paddd xmm1, xmm2
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movd r2d, xmm0
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and r2, 0ffffh ; effective low work truncated
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mov r3, r2
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imul r2, r3
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sar r2, $04
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movd retrd, xmm1
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sub retrd, r2d
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add r7,32
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add r7,r5
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%ifdef X86_32
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pop r6
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pop r5
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pop r4
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pop r3
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%endif
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POP_XMM
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ret
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;***********************************************************************
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; uint8_t MdInterAnalysisVaaInfo_sse41( int32_t *pSad8x8 )
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;***********************************************************************
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WELS_EXTERN MdInterAnalysisVaaInfo_sse41
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%assign push_num 0
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LOAD_1_PARA
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movdqa xmm0,[r0]
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pshufd xmm1, xmm0, 01Bh
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paddd xmm1, xmm0
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pshufd xmm2, xmm1, 0B1h
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paddd xmm1, xmm2
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psrad xmm1, 02h ; iAverageSad
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movdqa xmm2, xmm1
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psrad xmm2, 06h
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movdqa xmm3, xmm0 ; iSadBlock
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psrad xmm3, 06h
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psubd xmm3, xmm2
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pmulld xmm3, xmm3 ; [comment]: pmulld from SSE4.1 instruction sets
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pshufd xmm4, xmm3, 01Bh
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paddd xmm4, xmm3
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pshufd xmm3, xmm4, 0B1h
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paddd xmm3, xmm4
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movd r0d, xmm3
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cmp r0d, 20 ; INTER_VARIANCE_SAD_THRESHOLD
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jb near .threshold_exit
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pshufd xmm0, xmm0, 01Bh
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pcmpgtd xmm0, xmm1 ; iSadBlock > iAverageSad
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movmskps retrd, xmm0
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ret
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.threshold_exit:
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mov retrd, 15
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ret
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;***********************************************************************
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; uint8_t MdInterAnalysisVaaInfo_sse2( int32_t *pSad8x8 )
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;***********************************************************************
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WELS_EXTERN MdInterAnalysisVaaInfo_sse2
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%assign push_num 0
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LOAD_1_PARA
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movdqa xmm0, [r0]
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pshufd xmm1, xmm0, 01Bh
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paddd xmm1, xmm0
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pshufd xmm2, xmm1, 0B1h
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paddd xmm1, xmm2
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psrad xmm1, 02h ; iAverageSad
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movdqa xmm2, xmm1
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psrad xmm2, 06h
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movdqa xmm3, xmm0 ; iSadBlock
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psrad xmm3, 06h
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psubd xmm3, xmm2
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; to replace pmulld functionality as below
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movdqa xmm2, xmm3
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pmuludq xmm2, xmm3
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pshufd xmm4, xmm3, 0B1h
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pmuludq xmm4, xmm4
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movdqa xmm5, xmm2
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punpckldq xmm5, xmm4
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punpckhdq xmm2, xmm4
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punpcklqdq xmm5, xmm2
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pshufd xmm4, xmm5, 01Bh
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paddd xmm4, xmm5
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pshufd xmm5, xmm4, 0B1h
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paddd xmm5, xmm4
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movd r0d, xmm5
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cmp r0d, 20 ; INTER_VARIANCE_SAD_THRESHOLD
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jb near .threshold_exit
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pshufd xmm0, xmm0, 01Bh
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pcmpgtd xmm0, xmm1 ; iSadBlock > iAverageSad
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movmskps retrd, xmm0
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ret
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.threshold_exit:
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mov retrd, 15
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ret
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