mirror of https://github.com/NekoX-Dev/NekoX.git
498 lines
20 KiB
ArmAsm
Executable File
498 lines
20 KiB
ArmAsm
Executable File
/*
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* Copyright © 2009 Nokia Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Author: Siarhei Siamashka (siarhei.siamashka@nokia.com)
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*/
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/*
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* This file contains implementations of NEON optimized pixel processing
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* functions. There is no full and detailed tutorial, but some functions
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* (those which are exposing some new or interesting features) are
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* extensively commented and can be used as examples.
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*
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* You may want to have a look at the comments for following functions:
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* - pixman_composite_over_8888_0565_asm_neon
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* - pixman_composite_over_n_8_0565_asm_neon
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*/
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/* Prevent the stack from becoming executable for no reason... */
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#if defined(__linux__) && defined(__ELF__)
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.section .note.GNU-stack,"",%progbits
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#endif
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.text
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.fpu neon
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.arch armv7a
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.object_arch armv4
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.eabi_attribute 10, 0 /* suppress Tag_FP_arch */
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.eabi_attribute 12, 0 /* suppress Tag_Advanced_SIMD_arch */
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.arm
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.altmacro
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.p2align 2
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//#include "pixman-arm-asm.h"
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/* Supplementary macro for setting function attributes */
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.macro pixman_asm_function fname
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.func fname
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.global fname
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#ifdef __ELF__
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.hidden fname
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.type fname, %function
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#endif
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fname:
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.endm
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//#include "pixman-private.h"
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/*
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* The defines which are shared between C and assembly code
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*/
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/* bilinear interpolation precision (must be < 8) */
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#define BILINEAR_INTERPOLATION_BITS 7
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#define BILINEAR_INTERPOLATION_RANGE (1 << BILINEAR_INTERPOLATION_BITS)
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#include "pixman-arm-neon-asm.h"
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/* Global configuration options and preferences */
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/*
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* The code can optionally make use of unaligned memory accesses to improve
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* performance of handling leading/trailing pixels for each scanline.
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* Configuration variable RESPECT_STRICT_ALIGNMENT can be set to 0 for
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* example in linux if unaligned memory accesses are not configured to
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* generate.exceptions.
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*/
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.set RESPECT_STRICT_ALIGNMENT, 1
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/*
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* Set default prefetch type. There is a choice between the following options:
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*
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* PREFETCH_TYPE_NONE (may be useful for the ARM cores where PLD is set to work
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* as NOP to workaround some HW bugs or for whatever other reason)
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*
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* PREFETCH_TYPE_SIMPLE (may be useful for simple single-issue ARM cores where
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* advanced prefetch intruduces heavy overhead)
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*
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* PREFETCH_TYPE_ADVANCED (useful for superscalar cores such as ARM Cortex-A8
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* which can run ARM and NEON instructions simultaneously so that extra ARM
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* instructions do not add (many) extra cycles, but improve prefetch efficiency)
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*
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* Note: some types of function can't support advanced prefetch and fallback
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* to simple one (those which handle 24bpp pixels)
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*/
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.set PREFETCH_TYPE_DEFAULT, PREFETCH_TYPE_ADVANCED
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/* Prefetch distance in pixels for simple prefetch */
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.set PREFETCH_DISTANCE_SIMPLE, 64
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/*
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* Implementation of pixman_composite_over_8888_0565_asm_neon
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*
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* This function takes a8r8g8b8 source buffer, r5g6b5 destination buffer and
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* performs OVER compositing operation. Function fast_composite_over_8888_0565
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* from pixman-fast-path.c does the same in C and can be used as a reference.
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*
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* First we need to have some NEON assembly code which can do the actual
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* operation on the pixels and provide it to the template macro.
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*
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* Template macro quite conveniently takes care of emitting all the necessary
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* code for memory reading and writing (including quite tricky cases of
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* handling unaligned leading/trailing pixels), so we only need to deal with
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* the data in NEON registers.
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*
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* NEON registers allocation in general is recommented to be the following:
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* d0, d1, d2, d3 - contain loaded source pixel data
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* d4, d5, d6, d7 - contain loaded destination pixels (if they are needed)
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* d24, d25, d26, d27 - contain loading mask pixel data (if mask is used)
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* d28, d29, d30, d31 - place for storing the result (destination pixels)
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*
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* As can be seen above, four 64-bit NEON registers are used for keeping
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* intermediate pixel data and up to 8 pixels can be processed in one step
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* for 32bpp formats (16 pixels for 16bpp, 32 pixels for 8bpp).
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*
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* This particular function uses the following registers allocation:
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* d0, d1, d2, d3 - contain loaded source pixel data
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* d4, d5 - contain loaded destination pixels (they are needed)
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* d28, d29 - place for storing the result (destination pixels)
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*/
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/*
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* Step one. We need to have some code to do some arithmetics on pixel data.
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* This is implemented as a pair of macros: '*_head' and '*_tail'. When used
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* back-to-back, they take pixel data from {d0, d1, d2, d3} and {d4, d5},
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* perform all the needed calculations and write the result to {d28, d29}.
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* The rationale for having two macros and not just one will be explained
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* later. In practice, any single monolitic function which does the work can
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* be split into two parts in any arbitrary way without affecting correctness.
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*
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* There is one special trick here too. Common template macro can optionally
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* make our life a bit easier by doing R, G, B, A color components
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* deinterleaving for 32bpp pixel formats (and this feature is used in
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* 'pixman_composite_over_8888_0565_asm_neon' function). So it means that
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* instead of having 8 packed pixels in {d0, d1, d2, d3} registers, we
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* actually use d0 register for blue channel (a vector of eight 8-bit
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* values), d1 register for green, d2 for red and d3 for alpha. This
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* simple conversion can be also done with a few NEON instructions:
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*
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* Packed to planar conversion:
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* vuzp.8 d0, d1
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* vuzp.8 d2, d3
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* vuzp.8 d1, d3
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* vuzp.8 d0, d2
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*
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* Planar to packed conversion:
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* vzip.8 d0, d2
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* vzip.8 d1, d3
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* vzip.8 d2, d3
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* vzip.8 d0, d1
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*
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* But pixel can be loaded directly in planar format using VLD4.8 NEON
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* instruction. It is 1 cycle slower than VLD1.32, so this is not always
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* desirable, that's why deinterleaving is optional.
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*
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* But anyway, here is the code:
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*/
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/*
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* OK, now we got almost everything that we need. Using the above two
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* macros, the work can be done right. But now we want to optimize
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* it a bit. ARM Cortex-A8 is an in-order core, and benefits really
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* a lot from good code scheduling and software pipelining.
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*
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* Let's construct some code, which will run in the core main loop.
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* Some pseudo-code of the main loop will look like this:
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* head
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* while (...) {
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* tail
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* head
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* }
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* tail
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*
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* It may look a bit weird, but this setup allows to hide instruction
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* latencies better and also utilize dual-issue capability more
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* efficiently (make pairs of load-store and ALU instructions).
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*
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* So what we need now is a '*_tail_head' macro, which will be used
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* in the core main loop. A trivial straightforward implementation
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* of this macro would look like this:
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*
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* pixman_composite_over_8888_0565_process_pixblock_tail
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* vst1.16 {d28, d29}, [DST_W, :128]!
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* vld1.16 {d4, d5}, [DST_R, :128]!
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* vld4.32 {d0, d1, d2, d3}, [SRC]!
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* pixman_composite_over_8888_0565_process_pixblock_head
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* cache_preload 8, 8
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*
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* Now it also got some VLD/VST instructions. We simply can't move from
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* processing one block of pixels to the other one with just arithmetics.
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* The previously processed data needs to be written to memory and new
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* data needs to be fetched. Fortunately, this main loop does not deal
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* with partial leading/trailing pixels and can load/store a full block
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* of pixels in a bulk. Additionally, destination buffer is already
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* 16 bytes aligned here (which is good for performance).
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*
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* New things here are DST_R, DST_W, SRC and MASK identifiers. These
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* are the aliases for ARM registers which are used as pointers for
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* accessing data. We maintain separate pointers for reading and writing
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* destination buffer (DST_R and DST_W).
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*
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* Another new thing is 'cache_preload' macro. It is used for prefetching
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* data into CPU L2 cache and improve performance when dealing with large
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* images which are far larger than cache size. It uses one argument
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* (actually two, but they need to be the same here) - number of pixels
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* in a block. Looking into 'pixman-arm-neon-asm.h' can provide some
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* details about this macro. Moreover, if good performance is needed
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* the code from this macro needs to be copied into '*_tail_head' macro
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* and mixed with the rest of code for optimal instructions scheduling.
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* We are actually doing it below.
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*
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* Now after all the explanations, here is the optimized code.
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* Different instruction streams (originaling from '*_head', '*_tail'
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* and 'cache_preload' macro) use different indentation levels for
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* better readability. Actually taking the code from one of these
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* indentation levels and ignoring a few VLD/VST instructions would
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* result in exactly the code from '*_head', '*_tail' or 'cache_preload'
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* macro!
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*/
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/*
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* And now the final part. We are using 'generate_composite_function' macro
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* to put all the stuff together. We are specifying the name of the function
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* which we want to get, number of bits per pixel for the source, mask and
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* destination (0 if unused, like mask in this case). Next come some bit
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* flags:
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* FLAG_DST_READWRITE - tells that the destination buffer is both read
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* and written, for write-only buffer we would use
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* FLAG_DST_WRITEONLY flag instead
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* FLAG_DEINTERLEAVE_32BPP - tells that we prefer to work with planar data
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* and separate color channels for 32bpp format.
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* The next things are:
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* - the number of pixels processed per iteration (8 in this case, because
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* that's the maximum what can fit into four 64-bit NEON registers).
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* - prefetch distance, measured in pixel blocks. In this case it is 5 times
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* by 8 pixels. That would be 40 pixels, or up to 160 bytes. Optimal
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* prefetch distance can be selected by running some benchmarks.
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*
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* After that we specify some macros, these are 'default_init',
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* 'default_cleanup' here which are empty (but it is possible to have custom
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* init/cleanup macros to be able to save/restore some extra NEON registers
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* like d8-d15 or do anything else) followed by
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* 'pixman_composite_over_8888_0565_process_pixblock_head',
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* 'pixman_composite_over_8888_0565_process_pixblock_tail' and
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* 'pixman_composite_over_8888_0565_process_pixblock_tail_head'
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* which we got implemented above.
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*
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* The last part is the NEON registers allocation scheme.
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*/
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/******************************************************************************/
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/******************************************************************************/
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.macro pixman_composite_out_reverse_8888_8888_process_pixblock_head
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vmvn.8 d24, d3 /* get inverted alpha */
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/* do alpha blending */
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vmull.u8 q8, d24, d4
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vmull.u8 q9, d24, d5
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vmull.u8 q10, d24, d6
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vmull.u8 q11, d24, d7
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.endm
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.macro pixman_composite_out_reverse_8888_8888_process_pixblock_tail
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vrshr.u16 q14, q8, #8
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vrshr.u16 q15, q9, #8
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vrshr.u16 q12, q10, #8
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vrshr.u16 q13, q11, #8
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vraddhn.u16 d28, q14, q8
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vraddhn.u16 d29, q15, q9
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vraddhn.u16 d30, q12, q10
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vraddhn.u16 d31, q13, q11
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.endm
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/******************************************************************************/
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.macro pixman_composite_over_8888_8888_process_pixblock_head
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pixman_composite_out_reverse_8888_8888_process_pixblock_head
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.endm
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.macro pixman_composite_over_8888_8888_process_pixblock_tail
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pixman_composite_out_reverse_8888_8888_process_pixblock_tail
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vqadd.u8 q14, q0, q14
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vqadd.u8 q15, q1, q15
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.endm
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.macro pixman_composite_over_8888_8888_process_pixblock_tail_head
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vld4.8 {d4, d5, d6, d7}, [DST_R, :128]!
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vrshr.u16 q14, q8, #8
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PF add PF_X, PF_X, #8
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PF tst PF_CTL, #0xF
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vrshr.u16 q15, q9, #8
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vrshr.u16 q12, q10, #8
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vrshr.u16 q13, q11, #8
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PF addne PF_X, PF_X, #8
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PF subne PF_CTL, PF_CTL, #1
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vraddhn.u16 d28, q14, q8
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vraddhn.u16 d29, q15, q9
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PF cmp PF_X, ORIG_W
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vraddhn.u16 d30, q12, q10
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vraddhn.u16 d31, q13, q11
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vqadd.u8 q14, q0, q14
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vqadd.u8 q15, q1, q15
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fetch_src_pixblock
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PF pld, [PF_SRC, PF_X, lsl #src_bpp_shift]
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vmvn.8 d22, d3
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PF pld, [PF_DST, PF_X, lsl #dst_bpp_shift]
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vst4.8 {d28, d29, d30, d31}, [DST_W, :128]!
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PF subge PF_X, PF_X, ORIG_W
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vmull.u8 q8, d22, d4
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PF subges PF_CTL, PF_CTL, #0x10
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vmull.u8 q9, d22, d5
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PF ldrgeb DUMMY, [PF_SRC, SRC_STRIDE, lsl #src_bpp_shift]!
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vmull.u8 q10, d22, d6
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PF ldrgeb DUMMY, [PF_DST, DST_STRIDE, lsl #dst_bpp_shift]!
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vmull.u8 q11, d22, d7
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.endm
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generate_composite_function \
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pixman_composite_over_8888_8888_asm_neon, 32, 0, 32, \
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FLAG_DST_READWRITE | FLAG_DEINTERLEAVE_32BPP, \
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8, /* number of pixels, processed in a single block */ \
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5, /* prefetch distance */ \
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default_init, \
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default_cleanup, \
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pixman_composite_over_8888_8888_process_pixblock_head, \
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pixman_composite_over_8888_8888_process_pixblock_tail, \
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pixman_composite_over_8888_8888_process_pixblock_tail_head
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generate_composite_function_single_scanline \
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pixman_composite_scanline_over_asm_neon, 32, 0, 32, \
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FLAG_DST_READWRITE | FLAG_DEINTERLEAVE_32BPP, \
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8, /* number of pixels, processed in a single block */ \
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default_init, \
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default_cleanup, \
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pixman_composite_over_8888_8888_process_pixblock_head, \
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pixman_composite_over_8888_8888_process_pixblock_tail, \
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pixman_composite_over_8888_8888_process_pixblock_tail_head
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/******************************************************************************/
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.macro pixman_composite_over_n_8888_process_pixblock_head
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/* deinterleaved source pixels in {d0, d1, d2, d3} */
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/* inverted alpha in {d24} */
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/* destination pixels in {d4, d5, d6, d7} */
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vmull.u8 q8, d24, d4
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vmull.u8 q9, d24, d5
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vmull.u8 q10, d24, d6
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vmull.u8 q11, d24, d7
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.endm
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.macro pixman_composite_over_n_8888_process_pixblock_tail
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vrshr.u16 q14, q8, #8
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vrshr.u16 q15, q9, #8
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vrshr.u16 q2, q10, #8
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vrshr.u16 q3, q11, #8
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vraddhn.u16 d28, q14, q8
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vraddhn.u16 d29, q15, q9
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vraddhn.u16 d30, q2, q10
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vraddhn.u16 d31, q3, q11
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vqadd.u8 q14, q0, q14
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vqadd.u8 q15, q1, q15
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.endm
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.macro pixman_composite_over_n_8888_process_pixblock_tail_head
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vrshr.u16 q14, q8, #8
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vrshr.u16 q15, q9, #8
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vrshr.u16 q2, q10, #8
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vrshr.u16 q3, q11, #8
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vraddhn.u16 d28, q14, q8
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vraddhn.u16 d29, q15, q9
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vraddhn.u16 d30, q2, q10
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vraddhn.u16 d31, q3, q11
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vld4.8 {d4, d5, d6, d7}, [DST_R, :128]!
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vqadd.u8 q14, q0, q14
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PF add PF_X, PF_X, #8
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PF tst PF_CTL, #0x0F
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PF addne PF_X, PF_X, #8
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PF subne PF_CTL, PF_CTL, #1
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vqadd.u8 q15, q1, q15
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PF cmp PF_X, ORIG_W
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vmull.u8 q8, d24, d4
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PF pld, [PF_DST, PF_X, lsl #dst_bpp_shift]
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vmull.u8 q9, d24, d5
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PF subge PF_X, PF_X, ORIG_W
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vmull.u8 q10, d24, d6
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PF subges PF_CTL, PF_CTL, #0x10
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vmull.u8 q11, d24, d7
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PF ldrgeb DUMMY, [PF_DST, DST_STRIDE, lsl #dst_bpp_shift]!
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vst4.8 {d28, d29, d30, d31}, [DST_W, :128]!
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.endm
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.macro pixman_composite_over_n_8888_init
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add DUMMY, sp, #ARGS_STACK_OFFSET
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vld1.32 {d3[0]}, [DUMMY]
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vdup.8 d0, d3[0]
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vdup.8 d1, d3[1]
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vdup.8 d2, d3[2]
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vdup.8 d3, d3[3]
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vmvn.8 d24, d3 /* get inverted alpha */
|
|
.endm
|
|
|
|
generate_composite_function \
|
|
pixman_composite_over_n_8888_asm_neon, 0, 0, 32, \
|
|
FLAG_DST_READWRITE | FLAG_DEINTERLEAVE_32BPP, \
|
|
8, /* number of pixels, processed in a single block */ \
|
|
5, /* prefetch distance */ \
|
|
pixman_composite_over_n_8888_init, \
|
|
default_cleanup, \
|
|
pixman_composite_over_8888_8888_process_pixblock_head, \
|
|
pixman_composite_over_8888_8888_process_pixblock_tail, \
|
|
pixman_composite_over_n_8888_process_pixblock_tail_head
|
|
|
|
/******************************************************************************/
|
|
|
|
.macro pixman_composite_src_n_8888_process_pixblock_head
|
|
.endm
|
|
|
|
.macro pixman_composite_src_n_8888_process_pixblock_tail
|
|
.endm
|
|
|
|
.macro pixman_composite_src_n_8888_process_pixblock_tail_head
|
|
vst1.32 {d0, d1, d2, d3}, [DST_W, :128]!
|
|
.endm
|
|
|
|
.macro pixman_composite_src_n_8888_init
|
|
add DUMMY, sp, #ARGS_STACK_OFFSET
|
|
vld1.32 {d0[0]}, [DUMMY]
|
|
vsli.u64 d0, d0, #32
|
|
vorr d1, d0, d0
|
|
vorr q1, q0, q0
|
|
.endm
|
|
|
|
.macro pixman_composite_src_n_8888_cleanup
|
|
.endm
|
|
|
|
generate_composite_function \
|
|
pixman_composite_src_n_8888_asm_neon, 0, 0, 32, \
|
|
FLAG_DST_WRITEONLY, \
|
|
8, /* number of pixels, processed in a single block */ \
|
|
0, /* prefetch distance */ \
|
|
pixman_composite_src_n_8888_init, \
|
|
pixman_composite_src_n_8888_cleanup, \
|
|
pixman_composite_src_n_8888_process_pixblock_head, \
|
|
pixman_composite_src_n_8888_process_pixblock_tail, \
|
|
pixman_composite_src_n_8888_process_pixblock_tail_head, \
|
|
0, /* dst_w_basereg */ \
|
|
0, /* dst_r_basereg */ \
|
|
0, /* src_basereg */ \
|
|
0 /* mask_basereg */
|
|
|
|
/******************************************************************************/
|
|
|
|
.macro pixman_composite_src_8888_8888_process_pixblock_head
|
|
.endm
|
|
|
|
.macro pixman_composite_src_8888_8888_process_pixblock_tail
|
|
.endm
|
|
|
|
.macro pixman_composite_src_8888_8888_process_pixblock_tail_head
|
|
vst1.32 {d0, d1, d2, d3}, [DST_W, :128]!
|
|
fetch_src_pixblock
|
|
cache_preload 8, 8
|
|
.endm
|
|
|
|
generate_composite_function \
|
|
pixman_composite_src_8888_8888_asm_neon, 32, 0, 32, \
|
|
FLAG_DST_WRITEONLY, \
|
|
8, /* number of pixels, processed in a single block */ \
|
|
10, /* prefetch distance */ \
|
|
default_init, \
|
|
default_cleanup, \
|
|
pixman_composite_src_8888_8888_process_pixblock_head, \
|
|
pixman_composite_src_8888_8888_process_pixblock_tail, \
|
|
pixman_composite_src_8888_8888_process_pixblock_tail_head, \
|
|
0, /* dst_w_basereg */ \
|
|
0, /* dst_r_basereg */ \
|
|
0, /* src_basereg */ \
|
|
0 /* mask_basereg */
|
|
|
|
/******************************************************************************/
|