1999-04-16 03:35:26 +02:00
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# Makefile template for Configure for the MIPS simulator.
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# Written by Cygnus Support.
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2003-05-16 09:11:43 +02:00
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SHELL = @SHELL@
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1999-04-16 03:35:26 +02:00
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## COMMON_PRE_CONFIG_FRAG
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srcdir=@srcdir@
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srcroot=$(srcdir)/../../
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# Object files created by various simulator generators.
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SIM_IGEN_OBJ = \
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support.o \
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itable.o \
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semantics.o \
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idecode.o \
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icache.o \
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@mips_igen_engine@ \
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irun.o \
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SIM_M16_OBJ = \
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m16_support.o \
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m16_semantics.o \
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m16_idecode.o \
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m16_icache.o \
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\
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m32_support.o \
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m32_semantics.o \
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m32_idecode.o \
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m32_icache.o \
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\
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itable.o \
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m16run.o \
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[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
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SIM_MICROMIPS_OBJ = \
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micromips16_support.o \
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micromips16_semantics.o \
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micromips16_idecode.o \
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micromips16_icache.o \
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\
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micromips32_support.o \
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micromips32_semantics.o \
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micromips32_idecode.o \
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micromips32_icache.o \
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\
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micromips_m32_support.o \
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micromips_m32_semantics.o \
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micromips_m32_idecode.o \
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micromips_m32_icache.o \
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\
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itable.o \
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micromipsrun.o \
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SIM_MULTI_OBJ = @sim_multi_obj@ \
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itable.o \
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multi-run.o \
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1999-04-16 03:35:26 +02:00
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MIPS_EXTRA_LIBS = @mips_extra_libs@
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SIM_OBJS = \
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2015-04-12 11:47:39 +02:00
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interp.o \
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1999-04-16 03:35:26 +02:00
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$(SIM_@sim_gen@_OBJ) \
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$(SIM_NEW_COMMON_OBJS) \
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2002-03-20 02:35:13 +01:00
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cp1.o \
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2002-06-02 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips.igen (mdmx): New (pseudo-)model.
* mdmx.c, mdmx.igen: New files.
* Makefile.in (SIM_OBJS): Add mdmx.o.
* sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
New typedefs.
(ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
(MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
(MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
(MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
(MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
(MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
(MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
(MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
(MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
(MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
(MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
(MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
(SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
(qh_fmtsel): New macros.
(_sim_cpu): New member "acc".
(mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
(mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
2002-06-02 09:39:26 +02:00
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mdmx.o \
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* Makefile.in (SIM_OBJS): Add dsp.o.
(dsp.o): New dependency.
(IGEN_INCLUDE): Add dsp.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
mipsisa64*-*-*): Add dsp to sim_igen_machine.
* configure: Regenerate.
* mips.igen: Add dsp model and include dsp.igen.
(MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
because these instructions are extended in DSP ASE.
* sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
adding 6 DSP accumulator registers and 1 DSP control register.
(AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
DSPCR_CCOND_SMASK): New define.
(DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
* dsp.c, dsp.igen: New files for MIPS DSP ASE.
2005-12-15 00:07:56 +01:00
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dsp.o \
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1999-04-16 03:35:26 +02:00
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sim-main.o \
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sim-resume.o \
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# List of flags to always pass to $(CC).
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SIM_SUBTARGET=@SIM_SUBTARGET@
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SIM_EXTRA_CFLAGS = $(SIM_SUBTARGET)
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SIM_EXTRA_CLEAN = clean-extra
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2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
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SIM_EXTRA_DISTCLEAN = distclean-extra
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1999-04-16 03:35:26 +02:00
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SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
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SIM_EXTRA_LIBS = $(MIPS_EXTRA_LIBS)
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## COMMON_POST_CONFIG_FRAG
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interp.o: $(srcdir)/interp.c config.h sim-main.h itable.h
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[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
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m16run.o: sim-main.h m16_idecode.h m32_idecode.h m16run.c $(SIM_EXTRA_DEPS)
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1999-04-16 03:35:26 +02:00
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[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
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micromipsrun.o: sim-main.h micromips16_idecode.h micromips32_idecode.h \
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micromips_m32_idecode.h micromipsrun.c $(SIM_EXTRA_DEPS)
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* Makefile.in (SIM_OBJS): Add dsp.o.
(dsp.o): New dependency.
(IGEN_INCLUDE): Add dsp.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
mipsisa64*-*-*): Add dsp to sim_igen_machine.
* configure: Regenerate.
* mips.igen: Add dsp model and include dsp.igen.
(MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
because these instructions are extended in DSP ASE.
* sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
adding 6 DSP accumulator registers and 1 DSP control register.
(AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
DSPCR_CCOND_SMASK): New define.
(DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
* dsp.c, dsp.igen: New files for MIPS DSP ASE.
2005-12-15 00:07:56 +01:00
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2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
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multi-run.o: multi-include.h tmp-mach-multi
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1999-04-16 03:35:26 +02:00
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../igen/igen:
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cd ../igen && $(MAKE)
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IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
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IGEN_INSN=$(srcdir)/mips.igen
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IGEN_DC=$(srcdir)/mips.dc
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M16_DC=$(srcdir)/m16.dc
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[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
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MICROMIPS32_DC=$(srcdir)/micromips.dc
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MICROMIPS16_DC=$(srcdir)/micromips16.dc
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1999-04-16 03:35:26 +02:00
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IGEN_INCLUDE=\
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[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
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$(srcdir)/micromipsdsp.igen \
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$(srcdir)/micromips.igen \
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1999-04-16 03:35:26 +02:00
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$(srcdir)/m16.igen \
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2006-08-29 14:38:45 +02:00
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$(srcdir)/m16e.igen \
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2002-06-03 20:35:19 +02:00
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$(srcdir)/mdmx.igen \
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2002-06-14 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips3d.igen: New file which contains MIPS-3D ASE instructions.
* Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
* mips.igen: Include mips3d.igen.
(mips3d): New model name for MIPS-3D ASE instructions.
(CVT.W.fmt): Don't use this instruction for word (source) format
instructions.
* cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
(fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
(fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
(NR_FRAC_GUARD, IMPLICIT_1): New macros.
* sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
(RSquareRoot1, RSquareRoot2): New macros.
(fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
(fp_rsqrt2): New functions.
* configure.in: Add MIPS-3D support to mipsisa64 simulator.
* configure: Regenerate.
2002-06-14 20:49:09 +02:00
|
|
|
$(srcdir)/mips3d.igen \
|
2002-06-03 23:00:29 +02:00
|
|
|
$(srcdir)/sb1.igen \
|
1999-04-16 03:35:26 +02:00
|
|
|
$(srcdir)/tx.igen \
|
|
|
|
|
$(srcdir)/vr.igen \
|
* Makefile.in (SIM_OBJS): Add dsp.o.
(dsp.o): New dependency.
(IGEN_INCLUDE): Add dsp.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
mipsisa64*-*-*): Add dsp to sim_igen_machine.
* configure: Regenerate.
* mips.igen: Add dsp model and include dsp.igen.
(MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
because these instructions are extended in DSP ASE.
* sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
adding 6 DSP accumulator registers and 1 DSP control register.
(AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
DSPCR_CCOND_SMASK): New define.
(DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
* dsp.c, dsp.igen: New files for MIPS DSP ASE.
2005-12-15 00:07:56 +01:00
|
|
|
$(srcdir)/dsp.igen \
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
$(srcdir)/dsp2.igen \
|
2006-08-29 14:38:45 +02:00
|
|
|
$(srcdir)/mips3264r2.igen \
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
# NB: Since these can be built by a number of generators, care
|
|
|
|
|
# must be taken to ensure that they are only dependant on
|
|
|
|
|
# one of those generators.
|
|
|
|
|
BUILT_SRC_FROM_GEN = \
|
|
|
|
|
itable.h \
|
|
|
|
|
itable.c \
|
|
|
|
|
|
|
|
|
|
SIM_IGEN_ALL = tmp-igen
|
|
|
|
|
SIM_M16_ALL = tmp-m16
|
[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
|
|
|
SIM_MICROMIPS_ALL = tmp-micromips
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
SIM_MULTI_ALL = tmp-multi
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BUILT_SRC_FROM_IGEN = \
|
|
|
|
|
icache.h \
|
|
|
|
|
icache.c \
|
|
|
|
|
idecode.h \
|
|
|
|
|
idecode.c \
|
|
|
|
|
semantics.h \
|
|
|
|
|
semantics.c \
|
|
|
|
|
model.h \
|
|
|
|
|
model.c \
|
|
|
|
|
support.h \
|
|
|
|
|
support.c \
|
|
|
|
|
engine.h \
|
|
|
|
|
engine.c \
|
|
|
|
|
irun.c \
|
|
|
|
|
|
|
|
|
|
$(BUILT_SRC_FROM_IGEN): tmp-igen
|
|
|
|
|
|
|
|
|
|
tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
|
|
|
|
|
cd ../igen && $(MAKE)
|
|
|
|
|
../igen/igen \
|
|
|
|
|
$(IGEN_TRACE) \
|
|
|
|
|
-I $(srcdir) \
|
|
|
|
|
-Werror \
|
|
|
|
|
-Wnodiscard \
|
|
|
|
|
@sim_igen_flags@ \
|
|
|
|
|
-G gen-direct-access \
|
|
|
|
|
-G gen-zero-r0 \
|
|
|
|
|
-B 32 \
|
|
|
|
|
-H 31 \
|
|
|
|
|
-i $(IGEN_INSN) \
|
|
|
|
|
-o $(IGEN_DC) \
|
|
|
|
|
-x \
|
|
|
|
|
-n icache.h -hc tmp-icache.h \
|
|
|
|
|
-n icache.c -c tmp-icache.c \
|
|
|
|
|
-n semantics.h -hs tmp-semantics.h \
|
|
|
|
|
-n semantics.c -s tmp-semantics.c \
|
|
|
|
|
-n idecode.h -hd tmp-idecode.h \
|
|
|
|
|
-n idecode.c -d tmp-idecode.c \
|
|
|
|
|
-n model.h -hm tmp-model.h \
|
|
|
|
|
-n model.c -m tmp-model.c \
|
|
|
|
|
-n support.h -hf tmp-support.h \
|
|
|
|
|
-n support.c -f tmp-support.c \
|
|
|
|
|
-n itable.h -ht tmp-itable.h \
|
|
|
|
|
-n itable.c -t tmp-itable.c \
|
|
|
|
|
-n engine.h -he tmp-engine.h \
|
|
|
|
|
-n engine.c -e tmp-engine.c \
|
|
|
|
|
-n irun.c -r tmp-irun.c
|
2003-05-16 09:11:43 +02:00
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h icache.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c icache.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h idecode.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c idecode.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h semantics.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c semantics.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h model.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c model.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h support.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c support.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-engine.h engine.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-engine.c engine.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-irun.c irun.c
|
1999-04-16 03:35:26 +02:00
|
|
|
touch tmp-igen
|
|
|
|
|
|
|
|
|
|
BUILT_SRC_FROM_M16 = \
|
|
|
|
|
m16_icache.h \
|
|
|
|
|
m16_icache.c \
|
|
|
|
|
m16_idecode.h \
|
|
|
|
|
m16_idecode.c \
|
|
|
|
|
m16_semantics.h \
|
|
|
|
|
m16_semantics.c \
|
|
|
|
|
m16_model.h \
|
|
|
|
|
m16_model.c \
|
|
|
|
|
m16_support.h \
|
|
|
|
|
m16_support.c \
|
|
|
|
|
\
|
|
|
|
|
m32_icache.h \
|
|
|
|
|
m32_icache.c \
|
|
|
|
|
m32_idecode.h \
|
|
|
|
|
m32_idecode.c \
|
|
|
|
|
m32_semantics.h \
|
|
|
|
|
m32_semantics.c \
|
|
|
|
|
m32_model.h \
|
|
|
|
|
m32_model.c \
|
|
|
|
|
m32_support.h \
|
|
|
|
|
m32_support.c \
|
|
|
|
|
|
|
|
|
|
$(BUILT_SRC_FROM_M16): tmp-m16
|
|
|
|
|
|
|
|
|
|
tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
|
|
|
|
|
cd ../igen && $(MAKE)
|
|
|
|
|
../igen/igen \
|
|
|
|
|
$(IGEN_TRACE) \
|
|
|
|
|
-I $(srcdir) \
|
|
|
|
|
-Werror \
|
|
|
|
|
-Wnodiscard \
|
|
|
|
|
@sim_m16_flags@ \
|
|
|
|
|
-G gen-direct-access \
|
|
|
|
|
-G gen-zero-r0 \
|
|
|
|
|
-B 16 \
|
|
|
|
|
-H 15 \
|
|
|
|
|
-i $(IGEN_INSN) \
|
|
|
|
|
-o $(M16_DC) \
|
|
|
|
|
-P m16_ \
|
|
|
|
|
-x \
|
|
|
|
|
-n m16_icache.h -hc tmp-icache.h \
|
|
|
|
|
-n m16_icache.c -c tmp-icache.c \
|
|
|
|
|
-n m16_semantics.h -hs tmp-semantics.h \
|
|
|
|
|
-n m16_semantics.c -s tmp-semantics.c \
|
|
|
|
|
-n m16_idecode.h -hd tmp-idecode.h \
|
|
|
|
|
-n m16_idecode.c -d tmp-idecode.c \
|
|
|
|
|
-n m16_model.h -hm tmp-model.h \
|
|
|
|
|
-n m16_model.c -m tmp-model.c \
|
|
|
|
|
-n m16_support.h -hf tmp-support.h \
|
|
|
|
|
-n m16_support.c -f tmp-support.c \
|
|
|
|
|
#
|
2003-05-16 09:11:43 +02:00
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h m16_icache.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m16_icache.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m16_idecode.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m16_idecode.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h m16_semantics.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c m16_semantics.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h m16_model.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c m16_model.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h m16_support.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c m16_support.c
|
1999-04-16 03:35:26 +02:00
|
|
|
../igen/igen \
|
|
|
|
|
$(IGEN_TRACE) \
|
|
|
|
|
-I $(srcdir) \
|
|
|
|
|
-Werror \
|
|
|
|
|
-Wnodiscard \
|
|
|
|
|
@sim_igen_flags@ \
|
|
|
|
|
-G gen-direct-access \
|
|
|
|
|
-G gen-zero-r0 \
|
|
|
|
|
-B 32 \
|
|
|
|
|
-H 31 \
|
|
|
|
|
-i $(IGEN_INSN) \
|
|
|
|
|
-o $(IGEN_DC) \
|
|
|
|
|
-P m32_ \
|
|
|
|
|
-x \
|
|
|
|
|
-n m32_icache.h -hc tmp-icache.h \
|
|
|
|
|
-n m32_icache.c -c tmp-icache.c \
|
|
|
|
|
-n m32_semantics.h -hs tmp-semantics.h \
|
|
|
|
|
-n m32_semantics.c -s tmp-semantics.c \
|
|
|
|
|
-n m32_idecode.h -hd tmp-idecode.h \
|
|
|
|
|
-n m32_idecode.c -d tmp-idecode.c \
|
|
|
|
|
-n m32_model.h -hm tmp-model.h \
|
|
|
|
|
-n m32_model.c -m tmp-model.c \
|
|
|
|
|
-n m32_support.h -hf tmp-support.h \
|
|
|
|
|
-n m32_support.c -f tmp-support.c \
|
|
|
|
|
#
|
2003-05-16 09:11:43 +02:00
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h m32_icache.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m32_icache.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m32_idecode.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m32_idecode.c
|
[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
|
|
|
|
|
m32_semantics.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
|
|
|
|
|
m32_semantics.c
|
2003-05-16 09:11:43 +02:00
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h m32_model.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c m32_model.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h m32_support.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c m32_support.c
|
1999-04-16 03:35:26 +02:00
|
|
|
../igen/igen \
|
|
|
|
|
$(IGEN_TRACE) \
|
|
|
|
|
-I $(srcdir) \
|
|
|
|
|
-Werror \
|
|
|
|
|
-Wnodiscard \
|
|
|
|
|
-Wnowidth \
|
|
|
|
|
@sim_igen_flags@ @sim_m16_flags@ \
|
|
|
|
|
-G gen-direct-access \
|
|
|
|
|
-G gen-zero-r0 \
|
|
|
|
|
-i $(IGEN_INSN) \
|
|
|
|
|
-n itable.h -ht tmp-itable.h \
|
|
|
|
|
-n itable.c -t tmp-itable.c \
|
|
|
|
|
#
|
2003-05-16 09:11:43 +02:00
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
|
1999-04-16 03:35:26 +02:00
|
|
|
touch tmp-m16
|
|
|
|
|
|
[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
|
|
|
BUILT_SRC_FROM_MICROMIPS = \
|
|
|
|
|
micromips16_icache.h \
|
|
|
|
|
micromips16_icache.c \
|
|
|
|
|
micromips16_idecode.h \
|
|
|
|
|
micromips16_idecode.c \
|
|
|
|
|
micromips16_semantics.h \
|
|
|
|
|
micromips16_semantics.c \
|
|
|
|
|
micromips16_model.h \
|
|
|
|
|
micromips16_model.c \
|
|
|
|
|
micromips16_support.h \
|
|
|
|
|
micromips16_support.c \
|
|
|
|
|
\
|
|
|
|
|
micromips32_icache.h \
|
|
|
|
|
micromips32_icache.c \
|
|
|
|
|
micromips32_idecode.h \
|
|
|
|
|
micromips32_idecode.c \
|
|
|
|
|
micromips32_semantics.h \
|
|
|
|
|
micromips32_semantics.c \
|
|
|
|
|
micromips32_model.h \
|
|
|
|
|
micromips32_model.c \
|
|
|
|
|
micromips32_support.h \
|
|
|
|
|
micromips32_support.c \
|
|
|
|
|
\
|
|
|
|
|
micromips_m32_icache.h \
|
|
|
|
|
micromips_m32_icache.c \
|
|
|
|
|
micromips_m32_idecode.h \
|
|
|
|
|
micromips_m32_idecode.c \
|
|
|
|
|
micromips_m32_semantics.h \
|
|
|
|
|
micromips_m32_semantics.c \
|
|
|
|
|
micromips_m32_model.h \
|
|
|
|
|
micromips_m32_model.c \
|
|
|
|
|
micromips_m32_support.h \
|
|
|
|
|
micromips_m32_support.c \
|
|
|
|
|
|
|
|
|
|
$(BUILT_SRC_FROM_MICROMIPS): tmp-micromips
|
|
|
|
|
|
|
|
|
|
tmp-micromips: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
|
|
|
|
|
cd ../igen && $(MAKE)
|
|
|
|
|
../igen/igen \
|
|
|
|
|
$(IGEN_TRACE) \
|
|
|
|
|
-I $(srcdir) \
|
|
|
|
|
-Werror \
|
|
|
|
|
-Wnodiscard \
|
|
|
|
|
@sim_micromips16_flags@ \
|
|
|
|
|
-G gen-direct-access \
|
|
|
|
|
-G gen-zero-r0 \
|
|
|
|
|
-B 16 \
|
|
|
|
|
-H 15 \
|
|
|
|
|
-i $(IGEN_INSN) \
|
|
|
|
|
-o $(MICROMIPS16_DC) \
|
|
|
|
|
-P micromips16_ \
|
|
|
|
|
-x \
|
|
|
|
|
-n micromips16_icache.h -hc tmp-icache.h \
|
|
|
|
|
-n micromips16_icache.c -c tmp-icache.c \
|
|
|
|
|
-n micromips16_semantics.h -hs tmp-semantics.h \
|
|
|
|
|
-n micromips16_semantics.c -s tmp-semantics.c \
|
|
|
|
|
-n micromips16_idecode.h -hd tmp-idecode.h \
|
|
|
|
|
-n micromips16_idecode.c -d tmp-idecode.c \
|
|
|
|
|
-n micromips16_model.h -hm tmp-model.h \
|
|
|
|
|
-n micromips16_model.c -m tmp-model.c \
|
|
|
|
|
-n micromips16_support.h -hf tmp-support.h \
|
|
|
|
|
-n micromips16_support.c -f tmp-support.c \
|
|
|
|
|
#
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
|
|
|
|
|
micromips16_icache.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
|
|
|
|
|
micromips16_icache.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
|
|
|
|
|
micromips16_idecode.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
|
|
|
|
|
micromips16_idecode.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
|
|
|
|
|
micromips16_semantics.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
|
|
|
|
|
micromips16_semantics.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
|
|
|
|
|
micromips16_model.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
|
|
|
|
|
micromips16_model.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
|
|
|
|
|
micromips16_support.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
|
|
|
|
|
micromips16_support.c
|
|
|
|
|
cd ../igen && $(MAKE)
|
|
|
|
|
../igen/igen \
|
|
|
|
|
$(IGEN_TRACE) \
|
|
|
|
|
-I $(srcdir) \
|
|
|
|
|
-Werror \
|
|
|
|
|
-Wnodiscard \
|
|
|
|
|
@sim_micromips_flags@ \
|
|
|
|
|
-G gen-direct-access \
|
|
|
|
|
-G gen-zero-r0 \
|
|
|
|
|
-B 32 \
|
|
|
|
|
-H 31 \
|
|
|
|
|
-i $(IGEN_INSN) \
|
|
|
|
|
-o $(MICROMIPS32_DC) \
|
|
|
|
|
-P micromips32_ \
|
|
|
|
|
-x \
|
|
|
|
|
-n micromips32_icache.h -hc tmp-icache.h \
|
|
|
|
|
-n micromips32_icache.c -c tmp-icache.c \
|
|
|
|
|
-n micromips32_semantics.h -hs tmp-semantics.h \
|
|
|
|
|
-n micromips32_semantics.c -s tmp-semantics.c \
|
|
|
|
|
-n micromips32_idecode.h -hd tmp-idecode.h \
|
|
|
|
|
-n micromips32_idecode.c -d tmp-idecode.c \
|
|
|
|
|
-n micromips32_model.h -hm tmp-model.h \
|
|
|
|
|
-n micromips32_model.c -m tmp-model.c \
|
|
|
|
|
-n micromips32_support.h -hf tmp-support.h \
|
|
|
|
|
-n micromips32_support.c -f tmp-support.c \
|
|
|
|
|
#
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
|
|
|
|
|
micromips32_icache.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
|
|
|
|
|
micromips32_icache.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
|
|
|
|
|
micromips32_idecode.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
|
|
|
|
|
micromips32_idecode.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
|
|
|
|
|
micromips32_semantics.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
|
|
|
|
|
micromips32_semantics.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
|
|
|
|
|
micromips32_model.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
|
|
|
|
|
micromips32_model.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
|
|
|
|
|
micromips32_support.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
|
|
|
|
|
micromips32_support.c
|
|
|
|
|
../igen/igen \
|
|
|
|
|
$(IGEN_TRACE) \
|
|
|
|
|
-I $(srcdir) \
|
|
|
|
|
-Werror \
|
|
|
|
|
-Wnodiscard \
|
|
|
|
|
@sim_igen_flags@ \
|
|
|
|
|
-G gen-direct-access \
|
|
|
|
|
-G gen-zero-r0 \
|
|
|
|
|
-B 32 \
|
|
|
|
|
-H 31 \
|
|
|
|
|
-i $(IGEN_INSN) \
|
|
|
|
|
-o $(IGEN_DC) \
|
|
|
|
|
-P micromips_m32_ \
|
|
|
|
|
-x \
|
|
|
|
|
-n micromips_m32_icache.h -hc tmp-icache.h \
|
|
|
|
|
-n micromips_m32_icache.c -c tmp-icache.c \
|
|
|
|
|
-n micromips_m32_semantics.h -hs tmp-semantics.h \
|
|
|
|
|
-n micromips_m32_semantics.c -s tmp-semantics.c \
|
|
|
|
|
-n micromips_m32_idecode.h -hd tmp-idecode.h \
|
|
|
|
|
-n micromips_m32_idecode.c -d tmp-idecode.c \
|
|
|
|
|
-n micromips_m32_model.h -hm tmp-model.h \
|
|
|
|
|
-n micromips_m32_model.c -m tmp-model.c \
|
|
|
|
|
-n micromips_m32_support.h -hf tmp-support.h \
|
|
|
|
|
-n micromips_m32_support.c -f tmp-support.c \
|
|
|
|
|
#
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
|
|
|
|
|
micromips_m32_icache.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
|
|
|
|
|
micromips_m32_icache.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
|
|
|
|
|
micromips_m32_idecode.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
|
|
|
|
|
micromips_m32_idecode.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
|
|
|
|
|
micromips_m32_semantics.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
|
|
|
|
|
micromips_m32_semantics.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
|
|
|
|
|
micromips_m32_model.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
|
|
|
|
|
micromips_m32_model.c
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
|
|
|
|
|
micromips_m32_support.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
|
|
|
|
|
micromips_m32_support.c
|
|
|
|
|
../igen/igen \
|
|
|
|
|
$(IGEN_TRACE) \
|
|
|
|
|
-I $(srcdir) \
|
|
|
|
|
-Werror \
|
|
|
|
|
-Wnodiscard \
|
|
|
|
|
-Wnowidth \
|
|
|
|
|
@sim_igen_flags@ @sim_micromips_flags@ @sim_micromips16_flags@\
|
|
|
|
|
-G gen-direct-access \
|
|
|
|
|
-G gen-zero-r0 \
|
|
|
|
|
-i $(IGEN_INSN) \
|
|
|
|
|
-n itable.h -ht tmp-itable.h \
|
|
|
|
|
-n itable.c -t tmp-itable.c \
|
|
|
|
|
#
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
|
|
|
|
|
touch tmp-micromips
|
1999-04-16 03:35:26 +02:00
|
|
|
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
BUILT_SRC_FROM_MULTI = @sim_multi_src@
|
|
|
|
|
SIM_MULTI_IGEN_CONFIGS = @sim_multi_igen_configs@
|
|
|
|
|
|
|
|
|
|
$(BUILT_SRC_FROM_MULTI): tmp-multi
|
|
|
|
|
tmp-multi: tmp-mach-multi tmp-itable-multi tmp-run-multi targ-vals.h
|
|
|
|
|
tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
|
|
|
|
|
for t in $(SIM_MULTI_IGEN_CONFIGS); do \
|
|
|
|
|
p=`echo $${t} | sed -e 's/:.*//'` ; \
|
|
|
|
|
m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
|
|
|
|
|
f=`echo $${t} | sed -e 's/.*://'` ; \
|
|
|
|
|
case $${p} in \
|
[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
|
|
|
micromips16*) e="-B 16 -H 15 -o $(MICROMIPS16_DC) -F 16" ;; \
|
|
|
|
|
micromips32* | micromips64*) \
|
|
|
|
|
e="-B 32 -H 31 -o $(MICROMIPS32_DC) -F $${f}" ;; \
|
|
|
|
|
micromips_m32*) \
|
|
|
|
|
e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}"; \
|
|
|
|
|
m="mips32r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \
|
|
|
|
|
micromips_m64*) \
|
|
|
|
|
e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}"; \
|
|
|
|
|
m="mips64r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
|
|
|
|
|
*) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
|
|
|
|
|
esac; \
|
|
|
|
|
../igen/igen \
|
|
|
|
|
$(IGEN_TRACE) \
|
|
|
|
|
$${e} \
|
|
|
|
|
-I $(srcdir) \
|
|
|
|
|
-Werror \
|
|
|
|
|
-Wnodiscard \
|
|
|
|
|
-N 0 \
|
|
|
|
|
-M $${m} \
|
|
|
|
|
-G gen-direct-access \
|
|
|
|
|
-G gen-zero-r0 \
|
|
|
|
|
-i $(IGEN_INSN) \
|
|
|
|
|
-P $${p}_ \
|
|
|
|
|
-x \
|
|
|
|
|
-n $${p}_icache.h -hc tmp-icache.h \
|
|
|
|
|
-n $${p}_icache.c -c tmp-icache.c \
|
|
|
|
|
-n $${p}_semantics.h -hs tmp-semantics.h \
|
|
|
|
|
-n $${p}_semantics.c -s tmp-semantics.c \
|
|
|
|
|
-n $${p}_idecode.h -hd tmp-idecode.h \
|
|
|
|
|
-n $${p}_idecode.c -d tmp-idecode.c \
|
|
|
|
|
-n $${p}_model.h -hm tmp-model.h \
|
|
|
|
|
-n $${p}_model.c -m tmp-model.c \
|
|
|
|
|
-n $${p}_support.h -hf tmp-support.h \
|
|
|
|
|
-n $${p}_support.c -f tmp-support.c \
|
|
|
|
|
-n $${p}_engine.h -he tmp-engine.h \
|
|
|
|
|
-n $${p}_engine.c -e tmp-engine.c \
|
2011-07-08 05:18:56 +02:00
|
|
|
|| exit; \
|
[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
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$${p}_icache.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
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$${p}_icache.c ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
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$${p}_idecode.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
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$${p}_idecode.c ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
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$${p}_semantics.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
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$${p}_semantics.c ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
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$${p}_model.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
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$${p}_model.c ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
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$${p}_support.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
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$${p}_support.c ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-engine.h \
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$${p}_engine.h ; \
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$(SHELL) $(srcdir)/../../move-if-change tmp-engine.c \
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$${p}_engine.c ; \
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2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
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done
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touch tmp-mach-multi
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tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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../igen/igen \
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$(IGEN_TRACE) \
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-I $(srcdir) \
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-Werror \
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-Wnodiscard \
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-Wnowidth \
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-N 0 \
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@sim_multi_flags@ \
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-G gen-direct-access \
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-G gen-zero-r0 \
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-i $(IGEN_INSN) \
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-n itable.h -ht tmp-itable.h \
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-n itable.c -t tmp-itable.c \
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#
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2003-05-16 09:11:43 +02:00
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$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
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$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
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2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
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touch tmp-itable-multi
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[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
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tmp-run-multi: $(srcdir)/m16run.c $(srcdir)/micromipsrun.c
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2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
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for t in $(SIM_MULTI_IGEN_CONFIGS); do \
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case $${t} in \
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2003-01-06 02:57:40 +01:00
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m16*) \
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2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
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m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \
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sed < $(srcdir)/m16run.c > tmp-run \
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-e "s/^sim_/m16$${m}_/" \
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-e "s/m16_/m16$${m}_/" \
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-e "s/m32_/m32$${m}_/" ; \
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[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-run \
|
|
|
|
|
m16$${m}_run.c ; \
|
|
|
|
|
;;\
|
|
|
|
|
micromips32*) \
|
|
|
|
|
m=`echo $${t} | sed -e 's/^micromips32//' -e 's/:.*//'`; \
|
|
|
|
|
sed < $(srcdir)/micromipsrun.c > tmp-run \
|
|
|
|
|
-e "s/^sim_/micromips32$${m}_/" \
|
|
|
|
|
-e "s/micromips16_/micromips16$${m}_/" \
|
|
|
|
|
-e "s/micromips32_/micromips32$${m}_/" \
|
|
|
|
|
-e "s/m32_/m32$${m}_/" ; \
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-run \
|
|
|
|
|
micromips$${m}_run.c ; \
|
|
|
|
|
;;\
|
|
|
|
|
micromips64*) \
|
|
|
|
|
m=`echo $${t} | sed -e 's/^micromips64//' -e 's/:.*//'`; \
|
|
|
|
|
sed < $(srcdir)/micromipsrun.c > tmp-run \
|
|
|
|
|
-e "s/^sim_/micromips64$${m}_/" \
|
|
|
|
|
-e "s/micromips16_/micromips16$${m}_/" \
|
|
|
|
|
-e "s/micromips32_/micromips64$${m}_/" \
|
|
|
|
|
-e "s/m32_/m64$${m}_/" ; \
|
|
|
|
|
$(SHELL) $(srcdir)/../../move-if-change tmp-run \
|
|
|
|
|
micromips$${m}_run.c ; \
|
|
|
|
|
;;\
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
esac \
|
|
|
|
|
done
|
|
|
|
|
touch tmp-run-multi
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
clean-extra:
|
|
|
|
|
rm -f $(BUILT_SRC_FROM_GEN)
|
|
|
|
|
rm -f $(BUILT_SRC_FROM_IGEN)
|
|
|
|
|
rm -f $(BUILT_SRC_FROM_M16)
|
[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
|
|
|
rm -f $(BUILT_SRC_FROM_MICROMIPS)
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
rm -f $(BUILT_SRC_FROM_MULTI)
|
1999-04-16 03:35:26 +02:00
|
|
|
rm -f tmp-*
|
[PATCH] Add micromips support to the MIPS simulator
2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
Ali Lown <ali.lown@imgtec.com>
sim/common/
* sim-bits.h (EXTEND6): New macro.
(EXTEND12): New macro.
(EXTEND25): New macro.
sim/mips/
* Makefile.in (tmp-micromips): New rule.
(tmp-mach-multi): Add support for micromips.
* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
that works for both mips64 and micromips64.
(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
micromips32.
Add build support for micromips.
* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
Refactored instruction code to use these functions.
* dsp2.igen: Refactored instruction code to use the new functions.
* interp.c (decode_coproc): Refactored to work with any instruction
encoding.
(isa_mode): New variable
(RSVD_INSTRUCTION): Changed to 0x00000039.
* m16.igen (BREAK16): Refactored instruction to use do_break16.
(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
* micromips.dc: New file.
* micromips.igen: New file.
* micromips16.dc: New file.
* micromipsdsp.igen: New file.
* micromipsrun.c: New file.
* mips.igen (do_swc1): Changed to work with any instruction encoding.
(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
do_trunc_fmt): New functions, refactored from existing instructions.
Refactored instruction code to use these functions.
(RSVD): Changed to use new reserved instruction.
(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32
and micromips64 models.
Added include for micromips.igen and micromipsdsp.igen
Add micromips32 and micromips64 models.
(DecodeCoproc): Updated to use new macro definition.
* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
do_seb, do_seh do_rdhwr, do_wsbh): New functions.
Refactored instruction code to use these functions.
* sim-main.h (CP0_operation): New enum.
(DecodeCoproc): Updated macro.
(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
(sim_state): Add isa_mode field.
sim/testsuite/sim/mips/
* basic.exp (run_micromips_test, run_sim_tests): New functions
Add support for micromips tests.
* hilo-hazard-4.s: New file.
* testutils.inc (_dowrite): Changed reserved instruction encoding.
(writemsg): Moved the la and li instructions before the data they are
assigned to, which prevents a bug where MIPS32 relocations are used instead
of micromips relocations when building for micromips.
2015-09-25 16:52:18 +02:00
|
|
|
rm -f micromips16*.o micromips32*.o m16*.o m32*.o itable*.o
|
1999-04-16 03:35:26 +02:00
|
|
|
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
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distclean-extra:
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rm -f multi-include.h multi-run.c
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