2012-08-13 16:52:54 +02:00
|
|
|
/* aarch64-asm.h -- Header file for aarch64-asm.c and aarch64-asm-2.c.
|
2016-01-01 12:25:12 +01:00
|
|
|
Copyright (C) 2012-2016 Free Software Foundation, Inc.
|
2012-08-13 16:52:54 +02:00
|
|
|
Contributed by ARM Ltd.
|
|
|
|
|
|
|
|
This file is part of the GNU opcodes library.
|
|
|
|
|
|
|
|
This library is free software; you can redistribute it and/or modify
|
|
|
|
it under the terms of the GNU General Public License as published by
|
|
|
|
the Free Software Foundation; either version 3, or (at your option)
|
|
|
|
any later version.
|
|
|
|
|
|
|
|
It is distributed in the hope that it will be useful, but WITHOUT
|
|
|
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
|
|
|
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
|
|
|
License for more details.
|
|
|
|
|
|
|
|
You should have received a copy of the GNU General Public License
|
|
|
|
along with this program; see the file COPYING3. If not,
|
|
|
|
see <http://www.gnu.org/licenses/>. */
|
|
|
|
|
|
|
|
#ifndef OPCODES_AARCH64_ASM_H
|
|
|
|
#define OPCODES_AARCH64_ASM_H
|
|
|
|
|
|
|
|
#include "aarch64-opc.h"
|
|
|
|
|
|
|
|
/* Given OPCODE, return the opcode entry that OPCODE aliases to, e.g.
|
|
|
|
given LSL, return UBFM. */
|
|
|
|
|
|
|
|
const aarch64_opcode* aarch64_find_real_opcode (const aarch64_opcode *);
|
|
|
|
|
|
|
|
/* Switch-table-based high-level operand inserter. */
|
|
|
|
|
|
|
|
const char* aarch64_insert_operand (const aarch64_operand *,
|
|
|
|
const aarch64_opnd_info *, aarch64_insn *,
|
|
|
|
const aarch64_inst *);
|
|
|
|
|
|
|
|
/* Operand inserters. */
|
|
|
|
|
|
|
|
#define AARCH64_DECL_OPD_INSERTER(x) \
|
|
|
|
const char* aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
|
|
|
|
aarch64_insn *, const aarch64_inst *)
|
|
|
|
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_regno);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_reglane);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_reglist);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist_r);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_ldst_elemlist);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_shift);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_imm);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_imm_half);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_modified);
|
2016-09-21 17:51:24 +02:00
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_fpimm);
|
2012-08-13 16:52:54 +02:00
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_fbits);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_aimm);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_limm);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_ft);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_addr_uimm12);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_simd_addr_post);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_cond);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_sysreg);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_barrier);
|
2015-12-11 11:11:27 +01:00
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_hint);
|
2012-08-13 16:52:54 +02:00
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_prfop);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 17:53:54 +02:00
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_sve_index);
|
|
|
|
AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
|
2012-08-13 16:52:54 +02:00
|
|
|
|
|
|
|
#undef AARCH64_DECL_OPD_INSERTER
|
|
|
|
|
|
|
|
#endif /* OPCODES_AARCH64_ASM_H */
|