2002-12-05 06:17:39 +01:00
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/* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.
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2016-01-01 05:33:14 +01:00
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Copyright (C) 2002-2016 Free Software Foundation, Inc.
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2002-12-05 06:17:39 +01:00
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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2007-08-23 20:08:50 +02:00
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the Free Software Foundation; either version 3 of the License, or
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2002-12-05 06:17:39 +01:00
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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2007-08-23 20:08:50 +02:00
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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2002-12-05 06:17:39 +01:00
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#ifndef MIPS_TDEP_H
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#define MIPS_TDEP_H
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2013-06-25 00:18:32 +02:00
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#include "objfiles.h"
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2003-04-12 Andrew Cagney <cagney@redhat.com>
* gdbarch.sh: Add missing opaque declarations.
* gdbarch.h: Regnerate.
* symtab.h: Add missing opaque declarations.
* value.h, target.h, symfile.h, stabsread.h: Ditto.
* x86-64-tdep.h, xmodem.h, monitor.h, typeprint.h: Ditto.
* srec.h, solib-svr4.h, source.h, inferior.h: Ditto.
* ser-unix.h, serial.h, remote-utils.h, gdbcore.h: Ditto.
* ppc-tdep.h, ocd.h, mips-tdep.h, gdbtypes.h: Ditto.
* buildsym.h, builtin-regs.h, linespec.h, language.h: Ditto.
* i387-tdep.h, gdbthread.h, event-top.h, gdb.h: Ditto.
* dwarf2cfi.h, doublest.h, disasm.h, cp-abi.h: Ditto.
* cli-out.h, c-lang.h, ax-gdb.h, arch-utils.h: Ditto.
* ada-lang.h, config/nm-lynx.h, config/nm-linux.h: Ditto.
* config/sparc/tm-sp64.h, config/rs6000/tm-rs6000.h: Ditto.
* config/pa/tm-hppah.h, config/m68k/tm-delta68.h: Ditto.
* cli/cli-setshow.h, cli/cli-script.h: Ditto.
2003-04-12 19:41:26 +02:00
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struct gdbarch;
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2011-01-09 04:20:33 +01:00
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/* All the possible MIPS ABIs. */
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2002-12-05 06:17:39 +01:00
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enum mips_abi
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{
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MIPS_ABI_UNKNOWN = 0,
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MIPS_ABI_N32,
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MIPS_ABI_O32,
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MIPS_ABI_N64,
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MIPS_ABI_O64,
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MIPS_ABI_EABI32,
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MIPS_ABI_EABI64,
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MIPS_ABI_LAST
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};
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/* Return the MIPS ABI associated with GDBARCH. */
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enum mips_abi mips_abi (struct gdbarch *gdbarch);
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gdb/
* NEWS: Add microMIPS support and "set mips compression",
"show mips compression" commands.
* mips-tdep.h (mips_isa): New enum.
(gdbarch_tdep): Add mips_isa.
(mips_pc_is_mips16): Update prototype.
(mips_pc_is_mips, mips_pc_is_micromips): New prototypes.
* mips-tdep.c (mips_compression_mips16): New variable.
(mips_compression_micromips): Likewise.
(mips_compression_strings): Likewise.
(mips_compression_string): Likewise.
(is_mips16_isa, is_micromips_isa): New functions.
(is_mips16_addr): Rename to...
(is_compact_addr): ... this.
(unmake_mips16_addr): Likewise to...
(unmake_compact_addr): ... this.
(make_mips16_addr): Likewise to...
(make_compact_addr): ... this.
(is_mips_addr, is_mips16_addr, is_micromips_addr): New
functions.
(mips_elf_make_msymbol_special): Handle microMIPS code.
(msymbol_is_special): Rename to...
(msymbol_is_mips16): ... this.
(mips_make_symbol_special, mips_pc_is_mips16): Update
accordingly.
(msymbol_is_mips, msymbol_is_micromips): New functions.
(mips16_to_32_reg): Rename to...
(mips_reg3_to_reg): ... this.
(mips_pc_is_mips, mips_pc_is_micromips): New functions.
(mips_pc_isa): Likewise.
(mips_read_pc, mips_unwind_pc, mips_write_pc): Handle microMIPS
code.
(mips_fetch_instruction): Pass return status instead of printing
an error message if requested. Handle microMIPS code. Bail out
on an invalid ISA.
(micromips_op): New macro.
(b0s4_imm, b0s5_imm, b0s5_reg, b0s7_imm, b0s10_imm): Likewise.
(b1s9_imm, b2s3_cc, b4s2_regl, b5s5_op, b5s5_reg): Likewise.
(b6s4_op, b7s3_reg): Likewise.
(b0s6_op, b0s11_op, b0s12_imm, b0s16_imm, b0s26_imm): Likewise.
(b6s10_ext, b11s5_reg, b12s4_op): Likewise.
(mips_insn_size): New function.
(mips32_next_pc): Update mips_fetch_instruction call.
(micromips_relative_offset7): New function.
(micromips_relative_offset10): Likewise.
(micromips_relative_offset16): Likewise.
(micromips_pc_insn_size): Likewise.
(micromips_bc1_pc): Likewise.
(micromips_next_pc): Likewise.
(unpack_mips16): Update mips_fetch_instruction call.
(extended_mips16_next_pc): Update according to change to
mips16_to_32_reg.
(mips_next_pc): Update mips_pc_is_mips16 call. Handle microMIPS
code.
(mips16_scan_prologue): Update mips_fetch_instruction call.
Update according to change to mips16_to_32_reg.
(mips_insn16_frame_sniffer): Update mips_pc_is_mips16 call.
(mips_insn16_frame_base_sniffer): Likewise.
(micromips_decode_imm9): New function.
(micromips_scan_prologue): Likewise.
(mips_micro_frame_cache): Likewise.
(mips_micro_frame_this_id): Likewise.
(mips_micro_frame_prev_register): Likewise.
(mips_micro_frame_sniffer): Likewise.
(mips_micro_frame_unwind): New variable.
(mips_micro_frame_base_address): New function.
(mips_micro_frame_base): New variable.
(mips_micro_frame_base_sniffer): New function.
(mips32_scan_prologue): Update mips_fetch_instruction call.
(mips_insn32_frame_sniffer): Check for the standard MIPS ISA
rather than for MIPS16.
(mips_insn32_frame_base_sniffer): Likewise.
(mips_addr_bits_remove): Handle microMIPS code.
(deal_with_atomic_sequence): Rename to...
(mips_deal_with_atomic_sequence): ... this. Update the type
of the variable used to hold an instruction. Remove the ISA bit
check. Update mips_fetch_instruction call.
(micromips_deal_with_atomic_sequence): New function.
(deal_with_atomic_sequence): Likewise.
(mips_about_to_return): Handle microMIPS code. Update
mips_fetch_instruction call.
(heuristic_proc_start): Check for the standard MIPS ISA rather
than for MIPS16. Update mips_pc_is_mips16 and
mips_fetch_instruction calls. Handle microMIPS code.
(mips_push_dummy_code): Handle microMIPS code.
(mips_eabi_push_dummy_call): Likewise.
(mips_o32_return_value): Update mips_pc_is_mips16 call.
(mips_o64_push_dummy_call): Handle microMIPS code.
(mips_o64_return_value): Update mips_pc_is_mips16 call.
(is_delayed): Remove function.
(mips_single_step_through_delay): Replace the call to is_delayed
with mips32_instruction_has_delay_slot. Correct MIPS16 handling.
Handle microMIPS code.
(mips_skip_prologue): Update mips_pc_is_mips16 call. Handle
microMIPS code.
(mips32_in_function_epilogue_p): Update mips_fetch_instruction
call.
(micromips_in_function_epilogue_p): New function.
(mips16_in_function_epilogue_p): Update mips_fetch_instruction
call.
(mips_in_function_epilogue_p): Update mips_pc_is_mips16 call.
Handle microMIPS.
(gdb_print_insn_mips): Likewise.
(mips_breakpoint_from_pc): Likewise.
(mips_remote_breakpoint_from_pc): New function.
(mips32_instruction_has_delay_slot): Simplify making use of the
updated mips_fetch_instruction interface.
(micromips_instruction_has_delay_slot): New function.
(mips16_instruction_has_delay_slot): Simplify making use of the
updated mips_fetch_instruction interface.
(mips_adjust_breakpoint_address): Check for the standard MIPS
ISA rather than for MIPS16 ISA. Update for unmake_compact_addr
calls. Handle microMIPS code.
(mips_get_mips16_fn_stub_pc): Update mips_fetch_instruction call.
(mips_skip_trampoline_code): Handle microMIPS code.
(global_mips_compression): New function.
(mips_gdbarch_init): Handle the compressed ISA setting from ELF
file flags. Register the microMIPS remote breakpoint handler
and heuristic frame unwinder.
(show_mips_compression): New function.
(_initialize_mips_tdep): Add the "set mips compression" and
"show mips compression" commands.
gdb/doc/
* gdb.texinfo (MIPS): Document "set mips compression" and "show
mips compression".
(MIPS Breakpoint Kinds): New subsubsection.
2012-05-19 01:46:40 +02:00
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/* Base and compressed MIPS ISA variations. */
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enum mips_isa
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{
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ISA_MIPS = -1, /* mips_compression_string depends on it. */
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ISA_MIPS16,
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ISA_MICROMIPS
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};
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2014-12-12 17:36:10 +01:00
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/* Corresponding MSYMBOL_TARGET_FLAG aliases. */
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#define MSYMBOL_TARGET_FLAG_MIPS16 MSYMBOL_TARGET_FLAG_1
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#define MSYMBOL_TARGET_FLAG_MICROMIPS MSYMBOL_TARGET_FLAG_2
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2004-04-29 20:28:43 +02:00
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/* Return the MIPS ISA's register size. Just a short cut to the BFD
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2003-11-15 23:09:07 +01:00
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architecture's word size. */
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2004-04-29 20:28:43 +02:00
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extern int mips_isa_regsize (struct gdbarch *gdbarch);
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2003-11-15 23:09:07 +01:00
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2003-11-16 Andrew Cagney <cagney@redhat.com>
* mips-tdep.c (struct gdbarch_tdep): Add field "regnum".
(mips_fpa0_regnum, mips_regnum): New function.
(mips_gdbarch_init): Fill in the "regnum" fields.
* mips-tdep.h (struct mips_regnum): Define.
(mips_regnum): Declare.
* config/mips/tm-mips.h (BADVADDR_REGNUM): Delete macro.
(LO_REGNUM, HI_REGNUM, BADVADDR_REGNUM): Ditto.
(CAUSE_REGNUM, PC_REGNUM, FP0_REGNUM): Ditto.
(FCRCS_REGNUM, FCRIR_REGNUM, FPA0_REGNUM): Ditto.
* config/mips/tm-irix6.h (FP0_REGNUM): Delete macro.
(PC_REGNUM, CAUSE_REGNUM, BADVADDR_REGNUM): Ditto.
(HI_REGNUM, LO_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): Ditto.
* config/mips/tm-irix5.h (FP0_REGNUM): Delete macro.
(PC_REGNUM, CAUSE_REGNUM, BADVADDR_REGNUM): Ditto.
(HI_REGNUM, LO_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): Ditto.
* remote-mips.c: Include "mips-tdep.h". Update.
* mipsnbsd-tdep.c: Update.
* mipsv4-nat.c: Update.
* mips-tdep.c: Update.
* mips-nat.c: Update.
* mips-linux-tdep.c: Update.
* mips-linux-nat.c: Update.
* irix5-nat.c: Update.
* dve3900-rom.c: Include "mips-tdep.h". Update.
(ignore_packet): Supress GCC warning.
* config/mips/nm-riscos.h: Update.
* Makefile.in (dve3900-rom.o, remote-mips.o): Update dependencies.
2003-11-16 20:24:05 +01:00
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/* Return the current index for various MIPS registers. */
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struct mips_regnum
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{
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int pc;
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int fp0;
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int fp_implementation_revision;
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int fp_control_status;
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int badvaddr; /* Bad vaddr for addressing exception. */
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int cause; /* Describes last exception. */
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int hi; /* Multiply/divide temp. */
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int lo; /* ... */
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gdb/
* features/mips-dsp.xml: New file.
* features/mips64-dsp.xml: New file.
* features/mips-dsp-linux.xml: New file.
* features/mips64-dsp-linux.xml: New file.
* features/Makefile (WHICH): Add mips-dsp-linux and
mips64-dsp-linux.
(mips-dsp-expedite, mips64-dsp-expedite): New variables.
* features/mips-dsp-linux.c: New file.
* features/mips64-dsp-linux.c: New file.
* regformats/mips-dsp-linux.dat: New file.
* regformats/mips64-dsp-linux.dat: New file.
* mips-linux-nat.c (mips_linux_register_addr): Handle DSP
registers.
(mips64_linux_register_addr): Likewise.
(mips64_linux_regsets_fetch_registers): Likewise.
(mips64_linux_regsets_store_registers): Likewise.
(mips64_linux_fetch_registers): Update call to
mips64_linux_regsets_fetch_registers.
(mips64_linux_store_registers): Update call to
mips64_linux_regsets_store_registers.
(mips_linux_read_description): Probe for DSP registers.
(_initialize_mips_linux_nat): Call initialize_tdesc_mips_dsp_linux
and initialize_tdesc_mips64_dsp_linux.
* mips-linux-tdep.c (supply_gregset, mips64_supply_gregset):
Remove padding of no longer used embedded register slots.
* mips-linux-tdep.h (DSP_BASE, DSP_CONTROL): New macros.
(MIPS_RESTART_REGNUM): Redefine enum value.
* mips-tdep.c (mips_generic_reg_names): Remove trailing null
strings.
(mips_tx39_reg_names): Likewise.
(mips_linux_reg_names): New array of register names for Linux
targets.
(mips_register_name): Check for a null pointer in
mips_processor_reg_names and return an empty string.
(mips_register_type): Exclude embedded registers for the IRIX
and Linux ABIs.
(mips_pseudo_register_type): Likewise. Use dynamic numbers to
refer to FP registers, LO, HI, BadVAddr, Cause and PC. Handle
DSP registers.
(mips_stab_reg_to_regnum): Handle DSP accumulators.
(mips_dwarf_dwarf2_ecoff_reg_to_regnum): Likewise.
(mips_gdbarch_init): Likewise. Initialize internal register
indices for the Linux ABI. Use dynamic numbers to refer to
registers, as applicable, while parsing the target description.
* mips-tdep.h (struct mips_regnum): Add dspacc/dspctl offsets.
gdb/doc/
* gdb.texinfo (MIPS Features): Add org.gnu.gdb.mips.dsp.
gdb/gdbserver/
* linux-low.h (linux_target_ops): Add regset_bitmap member.
* linux-low.c (use_linux_regsets): New macro.
[!HAVE_LINUX_REGSETS] (regsets_fetch_inferior_registers): Likewise.
[!HAVE_LINUX_REGSETS] (regsets_store_inferior_registers): Likewise.
(linux_register_in_regsets): New function.
(usr_fetch_inferior_registers): Skip registers covered by
regsets.
(usr_store_inferior_registers): Likewise.
(usr_fetch_inferior_registers): New macro.
(usr_store_inferior_registers): Likewise.
(linux_fetch_registers): Handle mixed regset/non-regset targets.
(linux_store_registers): Likewise.
* linux-mips-low.c (init_registers_mips_dsp_linux): New
prototype.
(init_registers_mips64_dsp_linux): Likewise.
(init_registers_mips_linux): New macro.
(init_registers_mips_dsp_linux): Likewise.
(mips_dsp_num_regs): Likewise.
(DSP_BASE, DSP_CONTROL): New fallback macros.
(mips_base_regs): New macro.
(mips_regmap): Use it. Fix the size.
(mips_dsp_regmap): New variable.
(mips_dsp_regset_bitmap): Likewise.
(mips_arch_setup): New function.
(mips_cannot_fetch_register): Use the_low_target.regmap rather
than mips_regmap.
(mips_cannot_store_register): Likewise.
(the_low_target): Update .arch_setup, .num_regs and .regmap
initializers. Add .regset_bitmap initializer.
* linux-arm-low.c (the_low_target): Add .regset_bitmap
initializer.
* linux-bfin-low.c (the_low_target): Likewise.
* linux-cris-low.c (the_low_target): Likewise.
* linux-crisv32-low.c (the_low_target): Likewise.
* linux-ia64-low.c (the_low_target): Likewise.
* linux-m32r-low.c (the_low_target): Likewise.
* linux-m68k-low.c (the_low_target): Likewise.
* linux-ppc-low.c (the_low_target): Likewise.
* linux-s390-low.c (the_low_target): Likewise.
* linux-sh-low.c (the_low_target): Likewise.
* linux-sparc-low.c (the_low_target): Likewise.
* linux-tic6x-low.c (the_low_target): Likewise.
* linux-x86-low.c (the_low_target): Likewise.
* linux-xtensa-low.c (the_low_target): Likewise.
* configure.srv <mips*-*-linux*>: Add mips-dsp-linux.o and
mips64-dsp-linux.o to srv_regobj. Add mips-dsp-linux.xml,
mips64-dsp-linux.xml, mips-dsp.xml and mips64-dsp.xml to
srv_xmlfiles.
* Makefile.in (mips-dsp-linux.o, mips-dsp-linux.c): New targets.
(mips64-dsp-linux.o, mips64-dsp-linux.c): Likewise.
gdb/testsuite/
* gdb.xml/tdesc-regs.exp: Add "mips-dsp.xml" to the list of MIPS
core registers.
2012-03-01 23:19:48 +01:00
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int dspacc; /* SmartMIPS/DSP accumulators. */
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int dspctl; /* DSP control. */
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2003-11-16 Andrew Cagney <cagney@redhat.com>
* mips-tdep.c (struct gdbarch_tdep): Add field "regnum".
(mips_fpa0_regnum, mips_regnum): New function.
(mips_gdbarch_init): Fill in the "regnum" fields.
* mips-tdep.h (struct mips_regnum): Define.
(mips_regnum): Declare.
* config/mips/tm-mips.h (BADVADDR_REGNUM): Delete macro.
(LO_REGNUM, HI_REGNUM, BADVADDR_REGNUM): Ditto.
(CAUSE_REGNUM, PC_REGNUM, FP0_REGNUM): Ditto.
(FCRCS_REGNUM, FCRIR_REGNUM, FPA0_REGNUM): Ditto.
* config/mips/tm-irix6.h (FP0_REGNUM): Delete macro.
(PC_REGNUM, CAUSE_REGNUM, BADVADDR_REGNUM): Ditto.
(HI_REGNUM, LO_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): Ditto.
* config/mips/tm-irix5.h (FP0_REGNUM): Delete macro.
(PC_REGNUM, CAUSE_REGNUM, BADVADDR_REGNUM): Ditto.
(HI_REGNUM, LO_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): Ditto.
* remote-mips.c: Include "mips-tdep.h". Update.
* mipsnbsd-tdep.c: Update.
* mipsv4-nat.c: Update.
* mips-tdep.c: Update.
* mips-nat.c: Update.
* mips-linux-tdep.c: Update.
* mips-linux-nat.c: Update.
* irix5-nat.c: Update.
* dve3900-rom.c: Include "mips-tdep.h". Update.
(ignore_packet): Supress GCC warning.
* config/mips/nm-riscos.h: Update.
* Makefile.in (dve3900-rom.o, remote-mips.o): Update dependencies.
2003-11-16 20:24:05 +01:00
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};
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extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch);
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2008-07-27 22:52:42 +02:00
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/* Some MIPS boards don't support floating point while others only
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support single-precision floating-point operations. */
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enum mips_fpu_type
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{
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MIPS_FPU_DOUBLE, /* Full double precision floating point. */
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MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
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MIPS_FPU_NONE /* No floating point. */
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};
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2011-01-09 04:20:33 +01:00
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/* MIPS specific per-architecture information. */
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2008-07-27 22:52:42 +02:00
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struct gdbarch_tdep
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{
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/* from the elf header */
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int elf_flags;
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/* mips options */
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enum mips_abi mips_abi;
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enum mips_abi found_abi;
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gdb/
* NEWS: Add microMIPS support and "set mips compression",
"show mips compression" commands.
* mips-tdep.h (mips_isa): New enum.
(gdbarch_tdep): Add mips_isa.
(mips_pc_is_mips16): Update prototype.
(mips_pc_is_mips, mips_pc_is_micromips): New prototypes.
* mips-tdep.c (mips_compression_mips16): New variable.
(mips_compression_micromips): Likewise.
(mips_compression_strings): Likewise.
(mips_compression_string): Likewise.
(is_mips16_isa, is_micromips_isa): New functions.
(is_mips16_addr): Rename to...
(is_compact_addr): ... this.
(unmake_mips16_addr): Likewise to...
(unmake_compact_addr): ... this.
(make_mips16_addr): Likewise to...
(make_compact_addr): ... this.
(is_mips_addr, is_mips16_addr, is_micromips_addr): New
functions.
(mips_elf_make_msymbol_special): Handle microMIPS code.
(msymbol_is_special): Rename to...
(msymbol_is_mips16): ... this.
(mips_make_symbol_special, mips_pc_is_mips16): Update
accordingly.
(msymbol_is_mips, msymbol_is_micromips): New functions.
(mips16_to_32_reg): Rename to...
(mips_reg3_to_reg): ... this.
(mips_pc_is_mips, mips_pc_is_micromips): New functions.
(mips_pc_isa): Likewise.
(mips_read_pc, mips_unwind_pc, mips_write_pc): Handle microMIPS
code.
(mips_fetch_instruction): Pass return status instead of printing
an error message if requested. Handle microMIPS code. Bail out
on an invalid ISA.
(micromips_op): New macro.
(b0s4_imm, b0s5_imm, b0s5_reg, b0s7_imm, b0s10_imm): Likewise.
(b1s9_imm, b2s3_cc, b4s2_regl, b5s5_op, b5s5_reg): Likewise.
(b6s4_op, b7s3_reg): Likewise.
(b0s6_op, b0s11_op, b0s12_imm, b0s16_imm, b0s26_imm): Likewise.
(b6s10_ext, b11s5_reg, b12s4_op): Likewise.
(mips_insn_size): New function.
(mips32_next_pc): Update mips_fetch_instruction call.
(micromips_relative_offset7): New function.
(micromips_relative_offset10): Likewise.
(micromips_relative_offset16): Likewise.
(micromips_pc_insn_size): Likewise.
(micromips_bc1_pc): Likewise.
(micromips_next_pc): Likewise.
(unpack_mips16): Update mips_fetch_instruction call.
(extended_mips16_next_pc): Update according to change to
mips16_to_32_reg.
(mips_next_pc): Update mips_pc_is_mips16 call. Handle microMIPS
code.
(mips16_scan_prologue): Update mips_fetch_instruction call.
Update according to change to mips16_to_32_reg.
(mips_insn16_frame_sniffer): Update mips_pc_is_mips16 call.
(mips_insn16_frame_base_sniffer): Likewise.
(micromips_decode_imm9): New function.
(micromips_scan_prologue): Likewise.
(mips_micro_frame_cache): Likewise.
(mips_micro_frame_this_id): Likewise.
(mips_micro_frame_prev_register): Likewise.
(mips_micro_frame_sniffer): Likewise.
(mips_micro_frame_unwind): New variable.
(mips_micro_frame_base_address): New function.
(mips_micro_frame_base): New variable.
(mips_micro_frame_base_sniffer): New function.
(mips32_scan_prologue): Update mips_fetch_instruction call.
(mips_insn32_frame_sniffer): Check for the standard MIPS ISA
rather than for MIPS16.
(mips_insn32_frame_base_sniffer): Likewise.
(mips_addr_bits_remove): Handle microMIPS code.
(deal_with_atomic_sequence): Rename to...
(mips_deal_with_atomic_sequence): ... this. Update the type
of the variable used to hold an instruction. Remove the ISA bit
check. Update mips_fetch_instruction call.
(micromips_deal_with_atomic_sequence): New function.
(deal_with_atomic_sequence): Likewise.
(mips_about_to_return): Handle microMIPS code. Update
mips_fetch_instruction call.
(heuristic_proc_start): Check for the standard MIPS ISA rather
than for MIPS16. Update mips_pc_is_mips16 and
mips_fetch_instruction calls. Handle microMIPS code.
(mips_push_dummy_code): Handle microMIPS code.
(mips_eabi_push_dummy_call): Likewise.
(mips_o32_return_value): Update mips_pc_is_mips16 call.
(mips_o64_push_dummy_call): Handle microMIPS code.
(mips_o64_return_value): Update mips_pc_is_mips16 call.
(is_delayed): Remove function.
(mips_single_step_through_delay): Replace the call to is_delayed
with mips32_instruction_has_delay_slot. Correct MIPS16 handling.
Handle microMIPS code.
(mips_skip_prologue): Update mips_pc_is_mips16 call. Handle
microMIPS code.
(mips32_in_function_epilogue_p): Update mips_fetch_instruction
call.
(micromips_in_function_epilogue_p): New function.
(mips16_in_function_epilogue_p): Update mips_fetch_instruction
call.
(mips_in_function_epilogue_p): Update mips_pc_is_mips16 call.
Handle microMIPS.
(gdb_print_insn_mips): Likewise.
(mips_breakpoint_from_pc): Likewise.
(mips_remote_breakpoint_from_pc): New function.
(mips32_instruction_has_delay_slot): Simplify making use of the
updated mips_fetch_instruction interface.
(micromips_instruction_has_delay_slot): New function.
(mips16_instruction_has_delay_slot): Simplify making use of the
updated mips_fetch_instruction interface.
(mips_adjust_breakpoint_address): Check for the standard MIPS
ISA rather than for MIPS16 ISA. Update for unmake_compact_addr
calls. Handle microMIPS code.
(mips_get_mips16_fn_stub_pc): Update mips_fetch_instruction call.
(mips_skip_trampoline_code): Handle microMIPS code.
(global_mips_compression): New function.
(mips_gdbarch_init): Handle the compressed ISA setting from ELF
file flags. Register the microMIPS remote breakpoint handler
and heuristic frame unwinder.
(show_mips_compression): New function.
(_initialize_mips_tdep): Add the "set mips compression" and
"show mips compression" commands.
gdb/doc/
* gdb.texinfo (MIPS): Document "set mips compression" and "show
mips compression".
(MIPS Breakpoint Kinds): New subsubsection.
2012-05-19 01:46:40 +02:00
|
|
|
enum mips_isa mips_isa;
|
2008-07-27 22:52:42 +02:00
|
|
|
enum mips_fpu_type mips_fpu_type;
|
|
|
|
int mips_last_arg_regnum;
|
|
|
|
int mips_last_fp_arg_regnum;
|
|
|
|
int default_mask_address_p;
|
|
|
|
/* Is the target using 64-bit raw integer registers but only
|
|
|
|
storing a left-aligned 32-bit value in each? */
|
|
|
|
int mips64_transfers_32bit_regs_p;
|
|
|
|
/* Indexes for various registers. IRIX and embedded have
|
|
|
|
different values. This contains the "public" fields. Don't
|
|
|
|
add any that do not need to be public. */
|
|
|
|
const struct mips_regnum *regnum;
|
|
|
|
/* Register names table for the current register set. */
|
|
|
|
const char **mips_processor_reg_names;
|
|
|
|
|
|
|
|
/* The size of register data available from the target, if known.
|
|
|
|
This doesn't quite obsolete the manual
|
|
|
|
mips64_transfers_32bit_regs_p, since that is documented to force
|
|
|
|
left alignment even for big endian (very strange). */
|
|
|
|
int register_size_valid_p;
|
|
|
|
int register_size;
|
|
|
|
|
|
|
|
/* Return the expected next PC if FRAME is stopped at a syscall
|
|
|
|
instruction. */
|
|
|
|
CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
|
|
|
|
};
|
|
|
|
|
2007-05-13 14:48:40 +02:00
|
|
|
/* Register numbers of various important registers. */
|
2004-10-31 00:36:34 +02:00
|
|
|
|
2004-10-26 21:40:39 +02:00
|
|
|
enum
|
|
|
|
{
|
2004-10-31 00:36:34 +02:00
|
|
|
MIPS_ZERO_REGNUM = 0, /* Read-only register, always 0. */
|
2004-10-26 21:40:39 +02:00
|
|
|
MIPS_AT_REGNUM = 1,
|
2004-10-31 00:36:34 +02:00
|
|
|
MIPS_V0_REGNUM = 2, /* Function integer return value. */
|
2011-01-09 04:20:33 +01:00
|
|
|
MIPS_A0_REGNUM = 4, /* Loc of first arg during a subr call. */
|
2012-04-26 18:56:18 +02:00
|
|
|
MIPS_S2_REGNUM = 18, /* Contains return address in MIPS16 thunks. */
|
2004-10-31 00:36:34 +02:00
|
|
|
MIPS_T9_REGNUM = 25, /* Contains address of callee in PIC. */
|
2012-04-26 18:56:18 +02:00
|
|
|
MIPS_GP_REGNUM = 28,
|
2004-06-22 02:01:04 +02:00
|
|
|
MIPS_SP_REGNUM = 29,
|
2004-10-26 21:40:39 +02:00
|
|
|
MIPS_RA_REGNUM = 31,
|
2004-10-31 00:54:40 +02:00
|
|
|
MIPS_PS_REGNUM = 32, /* Contains processor status. */
|
2003-11-16 Andrew Cagney <cagney@redhat.com>
* mips-tdep.c (struct gdbarch_tdep): Add field "regnum".
(mips_fpa0_regnum, mips_regnum): New function.
(mips_gdbarch_init): Fill in the "regnum" fields.
* mips-tdep.h (struct mips_regnum): Define.
(mips_regnum): Declare.
* config/mips/tm-mips.h (BADVADDR_REGNUM): Delete macro.
(LO_REGNUM, HI_REGNUM, BADVADDR_REGNUM): Ditto.
(CAUSE_REGNUM, PC_REGNUM, FP0_REGNUM): Ditto.
(FCRCS_REGNUM, FCRIR_REGNUM, FPA0_REGNUM): Ditto.
* config/mips/tm-irix6.h (FP0_REGNUM): Delete macro.
(PC_REGNUM, CAUSE_REGNUM, BADVADDR_REGNUM): Ditto.
(HI_REGNUM, LO_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): Ditto.
* config/mips/tm-irix5.h (FP0_REGNUM): Delete macro.
(PC_REGNUM, CAUSE_REGNUM, BADVADDR_REGNUM): Ditto.
(HI_REGNUM, LO_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): Ditto.
* remote-mips.c: Include "mips-tdep.h". Update.
* mipsnbsd-tdep.c: Update.
* mipsv4-nat.c: Update.
* mips-tdep.c: Update.
* mips-nat.c: Update.
* mips-linux-tdep.c: Update.
* mips-linux-nat.c: Update.
* irix5-nat.c: Update.
* dve3900-rom.c: Include "mips-tdep.h". Update.
(ignore_packet): Supress GCC warning.
* config/mips/nm-riscos.h: Update.
* Makefile.in (dve3900-rom.o, remote-mips.o): Update dependencies.
2003-11-16 20:24:05 +01:00
|
|
|
MIPS_EMBED_LO_REGNUM = 33,
|
|
|
|
MIPS_EMBED_HI_REGNUM = 34,
|
|
|
|
MIPS_EMBED_BADVADDR_REGNUM = 35,
|
|
|
|
MIPS_EMBED_CAUSE_REGNUM = 36,
|
|
|
|
MIPS_EMBED_PC_REGNUM = 37,
|
2004-10-31 00:36:34 +02:00
|
|
|
MIPS_EMBED_FP0_REGNUM = 38,
|
2011-01-09 04:20:33 +01:00
|
|
|
MIPS_UNUSED_REGNUM = 73, /* Never used, FIXME. */
|
2004-10-31 01:08:18 +02:00
|
|
|
MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use. */
|
2004-10-31 01:22:54 +02:00
|
|
|
MIPS_PRID_REGNUM = 89, /* Processor ID. */
|
2004-10-31 01:08:18 +02:00
|
|
|
MIPS_LAST_EMBED_REGNUM = 89 /* Last one. */
|
2003-11-16 Andrew Cagney <cagney@redhat.com>
* mips-tdep.c (struct gdbarch_tdep): Add field "regnum".
(mips_fpa0_regnum, mips_regnum): New function.
(mips_gdbarch_init): Fill in the "regnum" fields.
* mips-tdep.h (struct mips_regnum): Define.
(mips_regnum): Declare.
* config/mips/tm-mips.h (BADVADDR_REGNUM): Delete macro.
(LO_REGNUM, HI_REGNUM, BADVADDR_REGNUM): Ditto.
(CAUSE_REGNUM, PC_REGNUM, FP0_REGNUM): Ditto.
(FCRCS_REGNUM, FCRIR_REGNUM, FPA0_REGNUM): Ditto.
* config/mips/tm-irix6.h (FP0_REGNUM): Delete macro.
(PC_REGNUM, CAUSE_REGNUM, BADVADDR_REGNUM): Ditto.
(HI_REGNUM, LO_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): Ditto.
* config/mips/tm-irix5.h (FP0_REGNUM): Delete macro.
(PC_REGNUM, CAUSE_REGNUM, BADVADDR_REGNUM): Ditto.
(HI_REGNUM, LO_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): Ditto.
* remote-mips.c: Include "mips-tdep.h". Update.
* mipsnbsd-tdep.c: Update.
* mipsv4-nat.c: Update.
* mips-tdep.c: Update.
* mips-nat.c: Update.
* mips-linux-tdep.c: Update.
* mips-linux-nat.c: Update.
* irix5-nat.c: Update.
* dve3900-rom.c: Include "mips-tdep.h". Update.
(ignore_packet): Supress GCC warning.
* config/mips/nm-riscos.h: Update.
* Makefile.in (dve3900-rom.o, remote-mips.o): Update dependencies.
2003-11-16 20:24:05 +01:00
|
|
|
};
|
|
|
|
|
2004-10-30 22:54:54 +02:00
|
|
|
/* Instruction sizes and other useful constants. */
|
|
|
|
enum
|
2004-10-26 21:40:39 +02:00
|
|
|
{
|
2004-10-30 22:54:54 +02:00
|
|
|
MIPS_INSN16_SIZE = 2,
|
|
|
|
MIPS_INSN32_SIZE = 4,
|
|
|
|
/* The number of floating-point or integer registers. */
|
|
|
|
MIPS_NUMREGS = 32
|
2004-10-26 21:40:39 +02:00
|
|
|
};
|
|
|
|
|
2004-10-26 16:13:24 +02:00
|
|
|
/* Single step based on where the current instruction will take us. */
|
2007-06-16 00:37:35 +02:00
|
|
|
extern int mips_software_single_step (struct frame_info *frame);
|
2003-11-16 23:46:49 +01:00
|
|
|
|
MIPS: Keep the ISA bit in compressed code addresses
1. Background information
The MIPS architecture, as originally designed and implemented in
mid-1980s has a uniform instruction word size that is 4 bytes, naturally
aligned. As such all MIPS instructions are located at addresses that
have their bits #1 and #0 set to zeroes, and any attempt to execute an
instruction from an address that has any of the two bits set to one
causes an address error exception. This may for example happen when a
jump-register instruction is executed whose register value used as the
jump target has any of these bits set.
Then in mid 1990s LSI sought a way to improve code density for their
TinyRISC family of MIPS cores and invented an alternatively encoded
instruction set in a joint effort with MIPS Technologies (then a
subsidiary of SGI). The new instruction set has been named the MIPS16
ASE (Application-Specific Extension) and uses a variable instruction
word size, which is 2 bytes (as the name of the ASE suggests) for most,
but there are a couple of exceptions that take 4 bytes, and then most of
the 2-byte instructions can be treated with a 2-byte extension prefix to
expand the range of the immediate operands used.
As a result instructions are no longer 4-byte aligned, instead they are
aligned to a multiple of 2. That left the bit #0 still unused for code
references, be it for the standard MIPS (i.e. as originally invented) or
for the MIPS16 instruction set, and based on that observation a clever
trick was invented that on one hand allowed the processor to be
seamlessly switched between the two instruction sets at any time at the
run time while on the other avoided the introduction of any special
control register to do that.
So it is the bit #0 of the instruction address that was chosen as the
selector and named the ISA bit. Any instruction executed at an even
address is interpreted as a standard MIPS instruction (the address still
has to have its bit #1 clear), any instruction executed at an odd
address is interpreted as a MIPS16 instruction.
To switch between modes ordinary jump instructions are used, such as
used for function calls and returns, specifically the bit #0 of the
source register used in jump-register instructions selects the execution
(ISA) mode for the following piece of code to be interpreted in.
Additionally new jump-immediate instructions were added that flipped the
ISA bit to select the opposite mode upon execution. They were
considered necessary to avoid the need to make register jumps in all
cases as the original jump-immediate instructions provided no way to
change the bit #0 at all.
This was all important for cases where standard MIPS and MIPS16 code had
to be mixed, either for compatibility with the existing binary code base
or to access resources not reachable from MIPS16 code (the MIPS16
instruction set only provides access to general-purpose registers, and
not for example floating-point unit registers or privileged coprocessor
0 registers) -- pieces of code in the opposite mode can be executed as
ordinary subroutine calls.
A similar approach has been more recently adopted for the MIPS16
replacement instruction set defined as the so called microMIPS ASE.
This is another instruction set encoding introduced to the MIPS
architecture. Just like the MIPS16 ASE, the microMIPS instruction set
uses a variable-length encoding, where each instruction takes a multiple
of 2 bytes. The ISA bit has been reused and for microMIPS-capable
processors selects between the standard MIPS and the microMIPS mode
instead.
2. Statement of the problem
To put it shortly, MIPS16 and microMIPS code pointers used by GDB are
different to these observed at the run time. This results in the same
expressions being evaluated producing different results in GDB and in
the program being debugged. Obviously it's the results obtained at the
run time that are correct (they define how the program behaves) and
therefore by definition the results obtained in GDB are incorrect.
A bit longer description will record that obviously at the run time the
ISA bit has to be set correctly (refer to background information above
if unsure why so) or the program will not run as expected. This is
recorded in all the executable file structures used at the run time: the
dynamic symbol table (but not always the static one!), the GOT, and
obviously in all the addresses embedded in code or data of the program
itself, calculated by applying the appropriate relocations at the static
link time.
While a program is being processed by GDB, the ISA bit is stripped off
from any code addresses, presumably to make them the same as the
respective raw memory byte address used by the processor to access the
instruction in the instruction fetch access cycle. This stripping is
actually performed outside GDB proper, in BFD, specifically
_bfd_mips_elf_symbol_processing (elfxx-mips.c, see the piece of code at
the very bottom of that function, starting with an: "If this is an
odd-valued function symbol, assume it's a MIPS16 or microMIPS one."
comment).
This function is also responsible for symbol table dumps made by
`objdump' too, so you'll never see the ISA bit reported there by that
tool, you need to use `readelf'.
This is however unlike what is ever done at the run time, the ISA bit
once present is never stripped off, for example a cast like this:
(short *) main
will not strip the ISA bit off and if the resulting pointer is intended
to be used to access instructions as data, for example for software
instruction decoding (like for fault recovery or emulation in a signal
handler) or for self-modifying code then the bit still has to be
stripped off by an explicit AND operation.
This is probably best illustrated with a simple real program example.
Let's consider the following simple program:
$ cat foobar.c
int __attribute__ ((mips16)) foo (void)
{
return 1;
}
int __attribute__ ((mips16)) bar (void)
{
return 2;
}
int __attribute__ ((nomips16)) foo32 (void)
{
return 3;
}
int (*foo32p) (void) = foo32;
int (*foop) (void) = foo;
int fooi = (int) foo;
int
main (void)
{
return foop ();
}
$
This is plain C with no odd tricks, except from the instruction mode
attributes. They are not necessary to trigger this problem, I just put
them here so that the program can be contained in a single source file
and to make it obvious which function is MIPS16 code and which is not.
Let's try it with Linux, so that everyone can repeat this experiment:
$ mips-linux-gnu-gcc -mips16 -g -O2 -o foobar foobar.c
$
Let's have a look at some interesting symbols:
$ mips-linux-gnu-readelf -s foobar | egrep 'table|foo|bar'
Symbol table '.dynsym' contains 7 entries:
Symbol table '.symtab' contains 95 entries:
55: 00000000 0 FILE LOCAL DEFAULT ABS foobar.c
66: 0040068c 4 FUNC GLOBAL DEFAULT [MIPS16] 12 bar
68: 00410848 4 OBJECT GLOBAL DEFAULT 21 foo32p
70: 00410844 4 OBJECT GLOBAL DEFAULT 21 foop
78: 00400684 8 FUNC GLOBAL DEFAULT 12 foo32
80: 00400680 4 FUNC GLOBAL DEFAULT [MIPS16] 12 foo
88: 00410840 4 OBJECT GLOBAL DEFAULT 21 fooi
$
Hmm, no sight of the ISA bit, but notice how foo and bar (but not
foo32!) have been marked as MIPS16 functions (ELF symbol structure's
`st_other' field is used for that).
So let's try to run and poke at this program with GDB. I'll be using a
native system for simplicity (I'll be using ellipses here and there to
remove unrelated clutter):
$ ./foobar
$ echo $?
1
$
So far, so good.
$ gdb ./foobar
[...]
(gdb) break main
Breakpoint 1 at 0x400490: file foobar.c, line 23.
(gdb) run
Starting program: .../foobar
Breakpoint 1, main () at foobar.c:23
23 return foop ();
(gdb)
Yay, it worked! OK, so let's poke at it:
(gdb) print main
$1 = {int (void)} 0x400490 <main>
(gdb) print foo32
$2 = {int (void)} 0x400684 <foo32>
(gdb) print foo32p
$3 = (int (*)(void)) 0x400684 <foo32>
(gdb) print bar
$4 = {int (void)} 0x40068c <bar>
(gdb) print foo
$5 = {int (void)} 0x400680 <foo>
(gdb) print foop
$6 = (int (*)(void)) 0x400681 <foo>
(gdb)
A-ha! Here's the difference and finally the ISA bit!
(gdb) print /x fooi
$7 = 0x400681
(gdb) p/x $pc
p/x $pc
$8 = 0x400491
(gdb)
And here as well...
(gdb) advance foo
foo () at foobar.c:4
4 }
(gdb) disassemble
Dump of assembler code for function foo:
0x00400680 <+0>: jr ra
0x00400682 <+2>: li v0,1
End of assembler dump.
(gdb) finish
Run till exit from #0 foo () at foobar.c:4
main () at foobar.c:24
24 }
Value returned is $9 = 1
(gdb) continue
Continuing.
[Inferior 1 (process 14103) exited with code 01]
(gdb)
So let's be a bit inquisitive...
(gdb) run
Starting program: .../foobar
Breakpoint 1, main () at foobar.c:23
23 return foop ();
(gdb)
Actually we do not like to run foo here at all. Let's run bar instead!
(gdb) set foop = bar
(gdb) print foop
$10 = (int (*)(void)) 0x40068c <bar>
(gdb)
Hmm, no ISA bit. Is it going to work?
(gdb) advance bar
bar () at foobar.c:9
9 }
(gdb) p/x $pc
$11 = 0x40068c
(gdb) disassemble
Dump of assembler code for function bar:
=> 0x0040068c <+0>: jr ra
0x0040068e <+2>: li v0,2
End of assembler dump.
(gdb) finish
Run till exit from #0 bar () at foobar.c:9
Program received signal SIGILL, Illegal instruction.
bar () at foobar.c:9
9 }
(gdb)
Oops!
(gdb) p/x $pc
$12 = 0x40068c
(gdb)
We're still there!
(gdb) continue
Continuing.
Program terminated with signal SIGILL, Illegal instruction.
The program no longer exists.
(gdb)
So let's try something else:
(gdb) run
Starting program: .../foobar
Breakpoint 1, main () at foobar.c:23
23 return foop ();
(gdb) set foop = foo
(gdb) advance foo
foo () at foobar.c:4
4 }
(gdb) disassemble
Dump of assembler code for function foo:
=> 0x00400680 <+0>: jr ra
0x00400682 <+2>: li v0,1
End of assembler dump.
(gdb) finish
Run till exit from #0 foo () at foobar.c:4
Program received signal SIGILL, Illegal instruction.
foo () at foobar.c:4
4 }
(gdb) continue
Continuing.
Program terminated with signal SIGILL, Illegal instruction.
The program no longer exists.
(gdb)
The same problem!
(gdb) run
Starting program:
/net/build2-lucid-cs/scratch/macro/mips-linux-fsf-gcc/isa-bit/foobar
Breakpoint 1, main () at foobar.c:23
23 return foop ();
(gdb) set foop = foo32
(gdb) advance foo32
foo32 () at foobar.c:14
14 }
(gdb) disassemble
Dump of assembler code for function foo32:
=> 0x00400684 <+0>: jr ra
0x00400688 <+4>: li v0,3
End of assembler dump.
(gdb) finish
Run till exit from #0 foo32 () at foobar.c:14
main () at foobar.c:24
24 }
Value returned is $14 = 3
(gdb) continue
Continuing.
[Inferior 1 (process 14113) exited with code 03]
(gdb)
That did work though, so it's the ISA bit only!
(gdb) quit
Enough!
That's the tip of the iceberg only though. So let's rebuild the
executable with some dynamic symbols:
$ mips-linux-gnu-gcc -mips16 -Wl,--export-dynamic -g -O2 -o foobar-dyn foobar.c
$ mips-linux-gnu-readelf -s foobar-dyn | egrep 'table|foo|bar'
Symbol table '.dynsym' contains 32 entries:
6: 004009cd 4 FUNC GLOBAL DEFAULT 12 bar
8: 00410b88 4 OBJECT GLOBAL DEFAULT 21 foo32p
9: 00410b84 4 OBJECT GLOBAL DEFAULT 21 foop
15: 004009c4 8 FUNC GLOBAL DEFAULT 12 foo32
17: 004009c1 4 FUNC GLOBAL DEFAULT 12 foo
25: 00410b80 4 OBJECT GLOBAL DEFAULT 21 fooi
Symbol table '.symtab' contains 95 entries:
55: 00000000 0 FILE LOCAL DEFAULT ABS foobar.c
69: 004009cd 4 FUNC GLOBAL DEFAULT 12 bar
71: 00410b88 4 OBJECT GLOBAL DEFAULT 21 foo32p
72: 00410b84 4 OBJECT GLOBAL DEFAULT 21 foop
79: 004009c4 8 FUNC GLOBAL DEFAULT 12 foo32
81: 004009c1 4 FUNC GLOBAL DEFAULT 12 foo
89: 00410b80 4 OBJECT GLOBAL DEFAULT 21 fooi
$
OK, now the ISA bit is there for a change, but the MIPS16 `st_other'
attribute gone, hmm... What does `objdump' do then:
$ mips-linux-gnu-objdump -Tt foobar-dyn | egrep 'SYMBOL|foo|bar'
foobar-dyn: file format elf32-tradbigmips
SYMBOL TABLE:
00000000 l df *ABS* 00000000 foobar.c
004009cc g F .text 00000004 0xf0 bar
00410b88 g O .data 00000004 foo32p
00410b84 g O .data 00000004 foop
004009c4 g F .text 00000008 foo32
004009c0 g F .text 00000004 0xf0 foo
00410b80 g O .data 00000004 fooi
DYNAMIC SYMBOL TABLE:
004009cc g DF .text 00000004 Base 0xf0 bar
00410b88 g DO .data 00000004 Base foo32p
00410b84 g DO .data 00000004 Base foop
004009c4 g DF .text 00000008 Base foo32
004009c0 g DF .text 00000004 Base 0xf0 foo
00410b80 g DO .data 00000004 Base fooi
$
Hmm, the attribute (0xf0, printed raw) is back, and the ISA bit gone
again.
Let's have a look at some DWARF-2 records GDB uses (I'll be stripping
off a lot here for brevity) -- debug info:
$ mips-linux-gnu-readelf -wi foobar
Contents of the .debug_info section:
[...]
Compilation Unit @ offset 0x88:
Length: 0xbb (32-bit)
Version: 4
Abbrev Offset: 62
Pointer Size: 4
<0><93>: Abbrev Number: 1 (DW_TAG_compile_unit)
<94> DW_AT_producer : (indirect string, offset: 0x19e): GNU C 4.8.0 20120513 (experimental) -meb -mips16 -march=mips32r2 -mhard-float -mllsc -mplt -mno-synci -mno-shared -mabi=32 -g -O2
<98> DW_AT_language : 1 (ANSI C)
<99> DW_AT_name : (indirect string, offset: 0x190): foobar.c
<9d> DW_AT_comp_dir : (indirect string, offset: 0x225): [...]
<a1> DW_AT_ranges : 0x0
<a5> DW_AT_low_pc : 0x0
<a9> DW_AT_stmt_list : 0x27
<1><ad>: Abbrev Number: 2 (DW_TAG_subprogram)
<ae> DW_AT_external : 1
<ae> DW_AT_name : foo
<b2> DW_AT_decl_file : 1
<b3> DW_AT_decl_line : 1
<b4> DW_AT_prototyped : 1
<b4> DW_AT_type : <0xc2>
<b8> DW_AT_low_pc : 0x400680
<bc> DW_AT_high_pc : 0x400684
<c0> DW_AT_frame_base : 1 byte block: 9c (DW_OP_call_frame_cfa)
<c2> DW_AT_GNU_all_call_sites: 1
<1><c2>: Abbrev Number: 3 (DW_TAG_base_type)
<c3> DW_AT_byte_size : 4
<c4> DW_AT_encoding : 5 (signed)
<c5> DW_AT_name : int
<1><c9>: Abbrev Number: 4 (DW_TAG_subprogram)
<ca> DW_AT_external : 1
<ca> DW_AT_name : (indirect string, offset: 0x18a): foo32
<ce> DW_AT_decl_file : 1
<cf> DW_AT_decl_line : 11
<d0> DW_AT_prototyped : 1
<d0> DW_AT_type : <0xc2>
<d4> DW_AT_low_pc : 0x400684
<d8> DW_AT_high_pc : 0x40068c
<dc> DW_AT_frame_base : 1 byte block: 9c (DW_OP_call_frame_cfa)
<de> DW_AT_GNU_all_call_sites: 1
<1><de>: Abbrev Number: 2 (DW_TAG_subprogram)
<df> DW_AT_external : 1
<df> DW_AT_name : bar
<e3> DW_AT_decl_file : 1
<e4> DW_AT_decl_line : 6
<e5> DW_AT_prototyped : 1
<e5> DW_AT_type : <0xc2>
<e9> DW_AT_low_pc : 0x40068c
<ed> DW_AT_high_pc : 0x400690
<f1> DW_AT_frame_base : 1 byte block: 9c (DW_OP_call_frame_cfa)
<f3> DW_AT_GNU_all_call_sites: 1
<1><f3>: Abbrev Number: 5 (DW_TAG_subprogram)
<f4> DW_AT_external : 1
<f4> DW_AT_name : (indirect string, offset: 0x199): main
<f8> DW_AT_decl_file : 1
<f9> DW_AT_decl_line : 21
<fa> DW_AT_prototyped : 1
<fa> DW_AT_type : <0xc2>
<fe> DW_AT_low_pc : 0x400490
<102> DW_AT_high_pc : 0x4004a4
<106> DW_AT_frame_base : 1 byte block: 9c (DW_OP_call_frame_cfa)
<108> DW_AT_GNU_all_tail_call_sites: 1
[...]
$
-- no sign of the ISA bit anywhere -- frame info:
$ mips-linux-gnu-readelf -wf foobar
[...]
Contents of the .debug_frame section:
00000000 0000000c ffffffff CIE
Version: 1
Augmentation: ""
Code alignment factor: 1
Data alignment factor: -4
Return address column: 31
DW_CFA_def_cfa_register: r29
DW_CFA_nop
00000010 0000000c 00000000 FDE cie=00000000 pc=00400680..00400684
00000020 0000000c 00000000 FDE cie=00000000 pc=00400684..0040068c
00000030 0000000c 00000000 FDE cie=00000000 pc=0040068c..00400690
00000040 00000018 00000000 FDE cie=00000000 pc=00400490..004004a4
DW_CFA_advance_loc: 6 to 00400496
DW_CFA_def_cfa_offset: 32
DW_CFA_offset: r31 at cfa-4
DW_CFA_advance_loc: 6 to 0040049c
DW_CFA_restore: r31
DW_CFA_def_cfa_offset: 0
DW_CFA_nop
DW_CFA_nop
DW_CFA_nop
[...]
$
-- no sign of the ISA bit anywhere -- range info (GDB doesn't use arange):
$ mips-linux-gnu-readelf -wR foobar
Contents of the .debug_ranges section:
Offset Begin End
00000000 00400680 00400690
00000000 00400490 004004a4
00000000 <End of list>
$
-- no sign of the ISA bit anywhere -- line info:
$ mips-linux-gnu-readelf -wl foobar
Raw dump of debug contents of section .debug_line:
[...]
Offset: 0x27
Length: 78
DWARF Version: 2
Prologue Length: 31
Minimum Instruction Length: 1
Initial value of 'is_stmt': 1
Line Base: -5
Line Range: 14
Opcode Base: 13
Opcodes:
Opcode 1 has 0 args
Opcode 2 has 1 args
Opcode 3 has 1 args
Opcode 4 has 1 args
Opcode 5 has 1 args
Opcode 6 has 0 args
Opcode 7 has 0 args
Opcode 8 has 0 args
Opcode 9 has 1 args
Opcode 10 has 0 args
Opcode 11 has 0 args
Opcode 12 has 1 args
The Directory Table is empty.
The File Name Table:
Entry Dir Time Size Name
1 0 0 0 foobar.c
Line Number Statements:
Extended opcode 2: set Address to 0x400681
Special opcode 6: advance Address by 0 to 0x400681 and Line by 1 to 2
Special opcode 7: advance Address by 0 to 0x400681 and Line by 2 to 4
Special opcode 55: advance Address by 3 to 0x400684 and Line by 8 to 12
Special opcode 7: advance Address by 0 to 0x400684 and Line by 2 to 14
Advance Line by -7 to 7
Special opcode 131: advance Address by 9 to 0x40068d and Line by 0 to 7
Special opcode 7: advance Address by 0 to 0x40068d and Line by 2 to 9
Advance PC by 3 to 0x400690
Extended opcode 1: End of Sequence
Extended opcode 2: set Address to 0x400491
Advance Line by 21 to 22
Copy
Special opcode 6: advance Address by 0 to 0x400491 and Line by 1 to 23
Special opcode 60: advance Address by 4 to 0x400495 and Line by -1 to 22
Special opcode 34: advance Address by 2 to 0x400497 and Line by 1 to 23
Special opcode 62: advance Address by 4 to 0x40049b and Line by 1 to 24
Special opcode 32: advance Address by 2 to 0x40049d and Line by -1 to 23
Special opcode 6: advance Address by 0 to 0x40049d and Line by 1 to 24
Advance PC by 7 to 0x4004a4
Extended opcode 1: End of Sequence
[...]
-- a-ha, the ISA bit is there! However it's not always right for some
reason, I don't have a small test case to show it, but here's an excerpt
from MIPS16 libc, a prologue of a function:
00019630 <__libc_init_first>:
19630: e8a0 jrc ra
19632: 6500 nop
00019634 <_init>:
19634: f000 6a11 li v0,17
19638: f7d8 0b08 la v1,15e00 <_DYNAMIC+0x15c54>
1963c: f400 3240 sll v0,16
19640: e269 addu v0,v1
19642: 659a move gp,v0
19644: 64f6 save 48,ra,s0-s1
19646: 671c move s0,gp
19648: d204 sw v0,16(sp)
1964a: f352 984c lw v0,-27828(s0)
1964e: 6724 move s1,a0
and the corresponding DWARF-2 line info:
Line Number Statements:
Extended opcode 2: set Address to 0x19631
Advance Line by 44 to 45
Copy
Special opcode 8: advance Address by 0 to 0x19631 and Line by 3 to 48
Special opcode 66: advance Address by 4 to 0x19635 and Line by 5 to 53
Advance PC by constant 17 to 0x19646
Special opcode 25: advance Address by 1 to 0x19647 and Line by 6 to 59
Advance Line by -6 to 53
Special opcode 33: advance Address by 2 to 0x19649 and Line by 0 to 53
Special opcode 39: advance Address by 2 to 0x1964b and Line by 6 to 59
Advance Line by -6 to 53
Special opcode 61: advance Address by 4 to 0x1964f and Line by 0 to 53
-- see that "Advance PC by constant 17" there? It clears the ISA bit,
however code at 0x19646 is not standard MIPS code at all. For some
reason the constant is always 17, I've never seen DW_LNS_const_add_pc
used with any other value -- is that a binutils bug or what?
3. Solution:
I think we should retain the value of the ISA bit in code references,
that is effectively treat them as cookies as they indeed are (although
trivially calculated) rather than raw memory byte addresses.
In a perfect world both the static symbol table and the respective
DWARF-2 records should be fixed to include the ISA bit in all the cases.
I think however that this is infeasible.
All the uses of `_bfd_mips_elf_symbol_processing' can not necessarily be
tracked down. This function is used by `elf_slurp_symbol_table' that in
turn is used by `bfd_canonicalize_symtab' and
`bfd_canonicalize_dynamic_symtab', which are public interfaces.
Similarly DWARF-2 records are used outside GDB, one notable if a bit
questionable is the exception unwinder (libgcc/unwind-dw2.c) -- I have
identified at least bits in `execute_cfa_program' and
`uw_frame_state_for', both around the calls to `_Unwind_IsSignalFrame',
that would need an update as they effectively flip the ISA bit freely;
see also the comment about MASK_RETURN_ADDR in gcc/config/mips/mips.h.
But there may be more places. Any change in how DWARF-2 records are
produced would require an update there and would cause compatibility
problems with libgcc.a binaries already distributed; given that this is
a static library a complex change involving function renames would
likely be required.
I propose therefore to accept the existing inconsistencies and deal with
them entirely within GDB. I have figured out that the ISA bit lost in
various places can still be recovered as long as we have symbol
information -- that'll have the `st_other' attribute correctly set to
one of standard MIPS/MIPS16/microMIPS encoding.
Here's the resulting change. It adds a couple of new `gdbarch' hooks,
one to update symbol information with the ISA bit lost in
`_bfd_mips_elf_symbol_processing', and two other ones to adjust DWARF-2
records as they're processed. The ISA bit is set in each address
handled according to information retrieved from the symbol table for the
symbol spanning the address if any; limits are adjusted based on the
address they point to related to the respective base address.
Additionally minimal symbol information has to be adjusted accordingly
in its gdbarch hook.
With these changes in place some complications with ISA bit juggling in
the PC that never fully worked can be removed from the MIPS backend.
Conversely, the generic dynamic linker event special breakpoint symbol
handler has to be updated to call the minimal symbol gdbarch hook to
record that the symbol is a MIPS16 or microMIPS address if applicable or
the breakpoint will be set at the wrong address and either fail to work
or cause SIGTRAPs (this is because the symbol is handled early on and
bypasses regular symbol processing).
4. Results obtained
The change fixes the example above -- to repeat only the crucial steps:
(gdb) break main
Breakpoint 1 at 0x400491: file foobar.c, line 23.
(gdb) run
Starting program: .../foobar
Breakpoint 1, main () at foobar.c:23
23 return foop ();
(gdb) print foo
$1 = {int (void)} 0x400681 <foo>
(gdb) set foop = bar
(gdb) advance bar
bar () at foobar.c:9
9 }
(gdb) disassemble
Dump of assembler code for function bar:
=> 0x0040068d <+0>: jr ra
0x0040068f <+2>: li v0,2
End of assembler dump.
(gdb) finish
Run till exit from #0 bar () at foobar.c:9
main () at foobar.c:24
24 }
Value returned is $2 = 2
(gdb) continue
Continuing.
[Inferior 1 (process 14128) exited with code 02]
(gdb)
-- excellent!
The change removes about 90 failures per MIPS16 multilib in mips-sde-elf
testing too, results for MIPS16 are now similar to that for standard
MIPS; microMIPS results are a bit worse because of host-I/O problems in
QEMU used instead of MIPSsim for microMIPS testing only:
=== gdb Summary ===
# of expected passes 14299
# of unexpected failures 187
# of expected failures 56
# of known failures 58
# of unresolved testcases 11
# of untested testcases 52
# of unsupported tests 174
MIPS16:
=== gdb Summary ===
# of expected passes 14298
# of unexpected failures 187
# of unexpected successes 2
# of expected failures 54
# of known failures 58
# of unresolved testcases 12
# of untested testcases 52
# of unsupported tests 174
microMIPS:
=== gdb Summary ===
# of expected passes 14149
# of unexpected failures 201
# of unexpected successes 2
# of expected failures 54
# of known failures 58
# of unresolved testcases 7
# of untested testcases 53
# of unsupported tests 175
2014-12-12 Maciej W. Rozycki <macro@codesourcery.com>
Maciej W. Rozycki <macro@mips.com>
Pedro Alves <pedro@codesourcery.com>
gdb/
* gdbarch.sh (elf_make_msymbol_special): Change type to `F',
remove `predefault' and `invalid_p' initializers.
(make_symbol_special): New architecture method.
(adjust_dwarf2_addr, adjust_dwarf2_line): Likewise.
(objfile, symbol): New declarations.
* arch-utils.h (default_elf_make_msymbol_special): Remove
prototype.
(default_make_symbol_special): New prototype.
(default_adjust_dwarf2_addr): Likewise.
(default_adjust_dwarf2_line): Likewise.
* mips-tdep.h (mips_unmake_compact_addr): New prototype.
* arch-utils.c (default_elf_make_msymbol_special): Remove
function.
(default_make_symbol_special): New function.
(default_adjust_dwarf2_addr): Likewise.
(default_adjust_dwarf2_line): Likewise.
* dwarf2-frame.c (decode_frame_entry_1): Call
`gdbarch_adjust_dwarf2_addr'.
* dwarf2loc.c (dwarf2_find_location_expression): Likewise.
* dwarf2read.c (create_addrmap_from_index): Likewise.
(process_psymtab_comp_unit_reader): Likewise.
(add_partial_symbol): Likewise.
(add_partial_subprogram): Likewise.
(process_full_comp_unit): Likewise.
(read_file_scope): Likewise.
(read_func_scope): Likewise. Call `gdbarch_make_symbol_special'.
(read_lexical_block_scope): Call `gdbarch_adjust_dwarf2_addr'.
(read_call_site_scope): Likewise.
(dwarf2_ranges_read): Likewise.
(dwarf2_record_block_ranges): Likewise.
(read_attribute_value): Likewise.
(dwarf_decode_lines_1): Call `gdbarch_adjust_dwarf2_line'.
(new_symbol_full): Call `gdbarch_adjust_dwarf2_addr'.
* elfread.c (elf_symtab_read): Don't call
`gdbarch_elf_make_msymbol_special' if unset.
* mips-linux-tdep.c (micromips_linux_sigframe_validate): Strip
the ISA bit from the PC.
* mips-tdep.c (mips_unmake_compact_addr): New function.
(mips_elf_make_msymbol_special): Set the ISA bit in the symbol's
address appropriately.
(mips_make_symbol_special): New function.
(mips_pc_is_mips): Set the ISA bit before symbol lookup.
(mips_pc_is_mips16): Likewise.
(mips_pc_is_micromips): Likewise.
(mips_pc_isa): Likewise.
(mips_adjust_dwarf2_addr): New function.
(mips_adjust_dwarf2_line): Likewise.
(mips_read_pc, mips_unwind_pc): Keep the ISA bit.
(mips_addr_bits_remove): Likewise.
(mips_skip_trampoline_code): Likewise.
(mips_write_pc): Don't set the ISA bit.
(mips_eabi_push_dummy_call): Likewise.
(mips_o64_push_dummy_call): Likewise.
(mips_gdbarch_init): Install `mips_make_symbol_special',
`mips_adjust_dwarf2_addr' and `mips_adjust_dwarf2_line' gdbarch
handlers.
* solib.c (gdb_bfd_lookup_symbol_from_symtab): Get
target-specific symbol address adjustments.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
2014-12-12 Maciej W. Rozycki <macro@codesourcery.com>
gdb/testsuite/
* gdb.base/func-ptrs.c: New file.
* gdb.base/func-ptrs.exp: New file.
2014-12-12 14:31:53 +01:00
|
|
|
/* Strip the ISA (compression) bit off from ADDR. */
|
|
|
|
extern CORE_ADDR mips_unmake_compact_addr (CORE_ADDR addr);
|
|
|
|
|
gdb/
* NEWS: Add microMIPS support and "set mips compression",
"show mips compression" commands.
* mips-tdep.h (mips_isa): New enum.
(gdbarch_tdep): Add mips_isa.
(mips_pc_is_mips16): Update prototype.
(mips_pc_is_mips, mips_pc_is_micromips): New prototypes.
* mips-tdep.c (mips_compression_mips16): New variable.
(mips_compression_micromips): Likewise.
(mips_compression_strings): Likewise.
(mips_compression_string): Likewise.
(is_mips16_isa, is_micromips_isa): New functions.
(is_mips16_addr): Rename to...
(is_compact_addr): ... this.
(unmake_mips16_addr): Likewise to...
(unmake_compact_addr): ... this.
(make_mips16_addr): Likewise to...
(make_compact_addr): ... this.
(is_mips_addr, is_mips16_addr, is_micromips_addr): New
functions.
(mips_elf_make_msymbol_special): Handle microMIPS code.
(msymbol_is_special): Rename to...
(msymbol_is_mips16): ... this.
(mips_make_symbol_special, mips_pc_is_mips16): Update
accordingly.
(msymbol_is_mips, msymbol_is_micromips): New functions.
(mips16_to_32_reg): Rename to...
(mips_reg3_to_reg): ... this.
(mips_pc_is_mips, mips_pc_is_micromips): New functions.
(mips_pc_isa): Likewise.
(mips_read_pc, mips_unwind_pc, mips_write_pc): Handle microMIPS
code.
(mips_fetch_instruction): Pass return status instead of printing
an error message if requested. Handle microMIPS code. Bail out
on an invalid ISA.
(micromips_op): New macro.
(b0s4_imm, b0s5_imm, b0s5_reg, b0s7_imm, b0s10_imm): Likewise.
(b1s9_imm, b2s3_cc, b4s2_regl, b5s5_op, b5s5_reg): Likewise.
(b6s4_op, b7s3_reg): Likewise.
(b0s6_op, b0s11_op, b0s12_imm, b0s16_imm, b0s26_imm): Likewise.
(b6s10_ext, b11s5_reg, b12s4_op): Likewise.
(mips_insn_size): New function.
(mips32_next_pc): Update mips_fetch_instruction call.
(micromips_relative_offset7): New function.
(micromips_relative_offset10): Likewise.
(micromips_relative_offset16): Likewise.
(micromips_pc_insn_size): Likewise.
(micromips_bc1_pc): Likewise.
(micromips_next_pc): Likewise.
(unpack_mips16): Update mips_fetch_instruction call.
(extended_mips16_next_pc): Update according to change to
mips16_to_32_reg.
(mips_next_pc): Update mips_pc_is_mips16 call. Handle microMIPS
code.
(mips16_scan_prologue): Update mips_fetch_instruction call.
Update according to change to mips16_to_32_reg.
(mips_insn16_frame_sniffer): Update mips_pc_is_mips16 call.
(mips_insn16_frame_base_sniffer): Likewise.
(micromips_decode_imm9): New function.
(micromips_scan_prologue): Likewise.
(mips_micro_frame_cache): Likewise.
(mips_micro_frame_this_id): Likewise.
(mips_micro_frame_prev_register): Likewise.
(mips_micro_frame_sniffer): Likewise.
(mips_micro_frame_unwind): New variable.
(mips_micro_frame_base_address): New function.
(mips_micro_frame_base): New variable.
(mips_micro_frame_base_sniffer): New function.
(mips32_scan_prologue): Update mips_fetch_instruction call.
(mips_insn32_frame_sniffer): Check for the standard MIPS ISA
rather than for MIPS16.
(mips_insn32_frame_base_sniffer): Likewise.
(mips_addr_bits_remove): Handle microMIPS code.
(deal_with_atomic_sequence): Rename to...
(mips_deal_with_atomic_sequence): ... this. Update the type
of the variable used to hold an instruction. Remove the ISA bit
check. Update mips_fetch_instruction call.
(micromips_deal_with_atomic_sequence): New function.
(deal_with_atomic_sequence): Likewise.
(mips_about_to_return): Handle microMIPS code. Update
mips_fetch_instruction call.
(heuristic_proc_start): Check for the standard MIPS ISA rather
than for MIPS16. Update mips_pc_is_mips16 and
mips_fetch_instruction calls. Handle microMIPS code.
(mips_push_dummy_code): Handle microMIPS code.
(mips_eabi_push_dummy_call): Likewise.
(mips_o32_return_value): Update mips_pc_is_mips16 call.
(mips_o64_push_dummy_call): Handle microMIPS code.
(mips_o64_return_value): Update mips_pc_is_mips16 call.
(is_delayed): Remove function.
(mips_single_step_through_delay): Replace the call to is_delayed
with mips32_instruction_has_delay_slot. Correct MIPS16 handling.
Handle microMIPS code.
(mips_skip_prologue): Update mips_pc_is_mips16 call. Handle
microMIPS code.
(mips32_in_function_epilogue_p): Update mips_fetch_instruction
call.
(micromips_in_function_epilogue_p): New function.
(mips16_in_function_epilogue_p): Update mips_fetch_instruction
call.
(mips_in_function_epilogue_p): Update mips_pc_is_mips16 call.
Handle microMIPS.
(gdb_print_insn_mips): Likewise.
(mips_breakpoint_from_pc): Likewise.
(mips_remote_breakpoint_from_pc): New function.
(mips32_instruction_has_delay_slot): Simplify making use of the
updated mips_fetch_instruction interface.
(micromips_instruction_has_delay_slot): New function.
(mips16_instruction_has_delay_slot): Simplify making use of the
updated mips_fetch_instruction interface.
(mips_adjust_breakpoint_address): Check for the standard MIPS
ISA rather than for MIPS16 ISA. Update for unmake_compact_addr
calls. Handle microMIPS code.
(mips_get_mips16_fn_stub_pc): Update mips_fetch_instruction call.
(mips_skip_trampoline_code): Handle microMIPS code.
(global_mips_compression): New function.
(mips_gdbarch_init): Handle the compressed ISA setting from ELF
file flags. Register the microMIPS remote breakpoint handler
and heuristic frame unwinder.
(show_mips_compression): New function.
(_initialize_mips_tdep): Add the "set mips compression" and
"show mips compression" commands.
gdb/doc/
* gdb.texinfo (MIPS): Document "set mips compression" and "show
mips compression".
(MIPS Breakpoint Kinds): New subsubsection.
2012-05-19 01:46:40 +02:00
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/* Tell if the program counter value in MEMADDR is in a standard
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MIPS function. */
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extern int mips_pc_is_mips (bfd_vma memaddr);
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2004-10-30 19:53:47 +02:00
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/* Tell if the program counter value in MEMADDR is in a MIPS16
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function. */
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gdb/
* NEWS: Add microMIPS support and "set mips compression",
"show mips compression" commands.
* mips-tdep.h (mips_isa): New enum.
(gdbarch_tdep): Add mips_isa.
(mips_pc_is_mips16): Update prototype.
(mips_pc_is_mips, mips_pc_is_micromips): New prototypes.
* mips-tdep.c (mips_compression_mips16): New variable.
(mips_compression_micromips): Likewise.
(mips_compression_strings): Likewise.
(mips_compression_string): Likewise.
(is_mips16_isa, is_micromips_isa): New functions.
(is_mips16_addr): Rename to...
(is_compact_addr): ... this.
(unmake_mips16_addr): Likewise to...
(unmake_compact_addr): ... this.
(make_mips16_addr): Likewise to...
(make_compact_addr): ... this.
(is_mips_addr, is_mips16_addr, is_micromips_addr): New
functions.
(mips_elf_make_msymbol_special): Handle microMIPS code.
(msymbol_is_special): Rename to...
(msymbol_is_mips16): ... this.
(mips_make_symbol_special, mips_pc_is_mips16): Update
accordingly.
(msymbol_is_mips, msymbol_is_micromips): New functions.
(mips16_to_32_reg): Rename to...
(mips_reg3_to_reg): ... this.
(mips_pc_is_mips, mips_pc_is_micromips): New functions.
(mips_pc_isa): Likewise.
(mips_read_pc, mips_unwind_pc, mips_write_pc): Handle microMIPS
code.
(mips_fetch_instruction): Pass return status instead of printing
an error message if requested. Handle microMIPS code. Bail out
on an invalid ISA.
(micromips_op): New macro.
(b0s4_imm, b0s5_imm, b0s5_reg, b0s7_imm, b0s10_imm): Likewise.
(b1s9_imm, b2s3_cc, b4s2_regl, b5s5_op, b5s5_reg): Likewise.
(b6s4_op, b7s3_reg): Likewise.
(b0s6_op, b0s11_op, b0s12_imm, b0s16_imm, b0s26_imm): Likewise.
(b6s10_ext, b11s5_reg, b12s4_op): Likewise.
(mips_insn_size): New function.
(mips32_next_pc): Update mips_fetch_instruction call.
(micromips_relative_offset7): New function.
(micromips_relative_offset10): Likewise.
(micromips_relative_offset16): Likewise.
(micromips_pc_insn_size): Likewise.
(micromips_bc1_pc): Likewise.
(micromips_next_pc): Likewise.
(unpack_mips16): Update mips_fetch_instruction call.
(extended_mips16_next_pc): Update according to change to
mips16_to_32_reg.
(mips_next_pc): Update mips_pc_is_mips16 call. Handle microMIPS
code.
(mips16_scan_prologue): Update mips_fetch_instruction call.
Update according to change to mips16_to_32_reg.
(mips_insn16_frame_sniffer): Update mips_pc_is_mips16 call.
(mips_insn16_frame_base_sniffer): Likewise.
(micromips_decode_imm9): New function.
(micromips_scan_prologue): Likewise.
(mips_micro_frame_cache): Likewise.
(mips_micro_frame_this_id): Likewise.
(mips_micro_frame_prev_register): Likewise.
(mips_micro_frame_sniffer): Likewise.
(mips_micro_frame_unwind): New variable.
(mips_micro_frame_base_address): New function.
(mips_micro_frame_base): New variable.
(mips_micro_frame_base_sniffer): New function.
(mips32_scan_prologue): Update mips_fetch_instruction call.
(mips_insn32_frame_sniffer): Check for the standard MIPS ISA
rather than for MIPS16.
(mips_insn32_frame_base_sniffer): Likewise.
(mips_addr_bits_remove): Handle microMIPS code.
(deal_with_atomic_sequence): Rename to...
(mips_deal_with_atomic_sequence): ... this. Update the type
of the variable used to hold an instruction. Remove the ISA bit
check. Update mips_fetch_instruction call.
(micromips_deal_with_atomic_sequence): New function.
(deal_with_atomic_sequence): Likewise.
(mips_about_to_return): Handle microMIPS code. Update
mips_fetch_instruction call.
(heuristic_proc_start): Check for the standard MIPS ISA rather
than for MIPS16. Update mips_pc_is_mips16 and
mips_fetch_instruction calls. Handle microMIPS code.
(mips_push_dummy_code): Handle microMIPS code.
(mips_eabi_push_dummy_call): Likewise.
(mips_o32_return_value): Update mips_pc_is_mips16 call.
(mips_o64_push_dummy_call): Handle microMIPS code.
(mips_o64_return_value): Update mips_pc_is_mips16 call.
(is_delayed): Remove function.
(mips_single_step_through_delay): Replace the call to is_delayed
with mips32_instruction_has_delay_slot. Correct MIPS16 handling.
Handle microMIPS code.
(mips_skip_prologue): Update mips_pc_is_mips16 call. Handle
microMIPS code.
(mips32_in_function_epilogue_p): Update mips_fetch_instruction
call.
(micromips_in_function_epilogue_p): New function.
(mips16_in_function_epilogue_p): Update mips_fetch_instruction
call.
(mips_in_function_epilogue_p): Update mips_pc_is_mips16 call.
Handle microMIPS.
(gdb_print_insn_mips): Likewise.
(mips_breakpoint_from_pc): Likewise.
(mips_remote_breakpoint_from_pc): New function.
(mips32_instruction_has_delay_slot): Simplify making use of the
updated mips_fetch_instruction interface.
(micromips_instruction_has_delay_slot): New function.
(mips16_instruction_has_delay_slot): Simplify making use of the
updated mips_fetch_instruction interface.
(mips_adjust_breakpoint_address): Check for the standard MIPS
ISA rather than for MIPS16 ISA. Update for unmake_compact_addr
calls. Handle microMIPS code.
(mips_get_mips16_fn_stub_pc): Update mips_fetch_instruction call.
(mips_skip_trampoline_code): Handle microMIPS code.
(global_mips_compression): New function.
(mips_gdbarch_init): Handle the compressed ISA setting from ELF
file flags. Register the microMIPS remote breakpoint handler
and heuristic frame unwinder.
(show_mips_compression): New function.
(_initialize_mips_tdep): Add the "set mips compression" and
"show mips compression" commands.
gdb/doc/
* gdb.texinfo (MIPS): Document "set mips compression" and "show
mips compression".
(MIPS Breakpoint Kinds): New subsubsection.
2012-05-19 01:46:40 +02:00
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extern int mips_pc_is_mips16 (struct gdbarch *gdbarch, bfd_vma memaddr);
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/* Tell if the program counter value in MEMADDR is in a microMIPS
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function. */
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extern int mips_pc_is_micromips (struct gdbarch *gdbarch, bfd_vma memaddr);
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2004-10-30 19:53:47 +02:00
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2011-01-09 04:20:33 +01:00
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/* Return the currently configured (or set) saved register size. */
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2004-10-30 22:11:36 +02:00
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extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);
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2012-05-18 14:43:05 +02:00
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/* Make PC the address of the next instruction to execute. */
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extern void mips_write_pc (struct regcache *regcache, CORE_ADDR pc);
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2007-09-10 23:14:11 +02:00
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/* Target descriptions which only indicate the size of general
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registers. */
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extern struct target_desc *mips_tdesc_gp32;
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extern struct target_desc *mips_tdesc_gp64;
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2013-06-25 00:18:32 +02:00
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/* Return non-zero if PC is in a MIPS SVR4 lazy binding stub section. */
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static inline int
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in_mips_stubs_section (CORE_ADDR pc)
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{
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return pc_in_section (pc, ".MIPS.stubs");
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}
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2002-12-05 06:17:39 +01:00
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#endif /* MIPS_TDEP_H */
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