2012-08-13 16:52:54 +02:00
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/* This file is automatically generated by aarch64-gen. Do not edit! */
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2016-01-01 12:25:12 +01:00
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/* Copyright (C) 2012-2016 Free Software Foundation, Inc.
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2012-08-13 16:52:54 +02:00
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Contributed by ARM Ltd.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#include "sysdep.h"
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#include "aarch64-asm.h"
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const aarch64_opcode *
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aarch64_find_real_opcode (const aarch64_opcode *opcode)
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{
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/* Use the index as the key to locate the real opcode. */
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int key = opcode - aarch64_opcode_table;
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int value;
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switch (key)
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{
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case 3: /* ngc */
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2015-11-27 16:02:26 +01:00
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case 2: /* sbc */
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2012-08-13 16:52:54 +02:00
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value = 2; /* --> sbc. */
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break;
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case 5: /* ngcs */
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2015-11-27 16:02:26 +01:00
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case 4: /* sbcs */
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2012-08-13 16:52:54 +02:00
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value = 4; /* --> sbcs. */
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break;
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case 8: /* cmn */
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2015-11-27 16:02:26 +01:00
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case 7: /* adds */
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2012-08-13 16:52:54 +02:00
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value = 7; /* --> adds. */
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break;
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case 11: /* cmp */
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2015-11-27 16:02:26 +01:00
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case 10: /* subs */
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2012-08-13 16:52:54 +02:00
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value = 10; /* --> subs. */
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break;
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case 13: /* mov */
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2015-11-27 16:02:26 +01:00
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case 12: /* add */
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2012-08-13 16:52:54 +02:00
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value = 12; /* --> add. */
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break;
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case 15: /* cmn */
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2015-11-27 16:02:26 +01:00
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case 14: /* adds */
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2012-08-13 16:52:54 +02:00
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value = 14; /* --> adds. */
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break;
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case 18: /* cmp */
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2015-11-27 16:02:26 +01:00
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case 17: /* subs */
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2012-08-13 16:52:54 +02:00
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value = 17; /* --> subs. */
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break;
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case 21: /* cmn */
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2015-11-27 16:02:26 +01:00
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case 20: /* adds */
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2012-08-13 16:52:54 +02:00
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value = 20; /* --> adds. */
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break;
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case 23: /* neg */
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2015-11-27 16:02:26 +01:00
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case 22: /* sub */
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2012-08-13 16:52:54 +02:00
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value = 22; /* --> sub. */
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break;
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case 26: /* negs */
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case 25: /* cmp */
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2015-11-27 16:02:26 +01:00
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case 24: /* subs */
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2012-08-13 16:52:54 +02:00
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value = 24; /* --> subs. */
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break;
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2015-12-14 18:22:36 +01:00
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case 150: /* mov */
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case 149: /* umov */
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value = 149; /* --> umov. */
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break;
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case 152: /* mov */
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case 151: /* ins */
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value = 151; /* --> ins. */
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break;
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case 154: /* mov */
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case 153: /* ins */
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value = 153; /* --> ins. */
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break;
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case 236: /* mvn */
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case 235: /* not */
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value = 235; /* --> not. */
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break;
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case 311: /* mov */
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case 310: /* orr */
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value = 310; /* --> orr. */
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break;
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case 380: /* sxtl */
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case 379: /* sshll */
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value = 379; /* --> sshll. */
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break;
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case 382: /* sxtl2 */
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case 381: /* sshll2 */
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value = 381; /* --> sshll2. */
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break;
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2015-12-14 18:40:03 +01:00
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case 404: /* uxtl */
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case 403: /* ushll */
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value = 403; /* --> ushll. */
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break;
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case 406: /* uxtl2 */
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case 405: /* ushll2 */
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value = 405; /* --> ushll2. */
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break;
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case 527: /* mov */
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case 526: /* dup */
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value = 526; /* --> dup. */
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break;
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2015-12-14 18:46:21 +01:00
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case 614: /* sxtw */
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case 613: /* sxth */
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case 612: /* sxtb */
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case 615: /* asr */
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case 611: /* sbfx */
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case 610: /* sbfiz */
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case 609: /* sbfm */
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value = 609; /* --> sbfm. */
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break;
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case 618: /* bfc */
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case 619: /* bfxil */
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case 617: /* bfi */
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case 616: /* bfm */
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value = 616; /* --> bfm. */
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break;
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case 624: /* uxth */
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case 623: /* uxtb */
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case 626: /* lsr */
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case 625: /* lsl */
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case 622: /* ubfx */
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case 621: /* ubfiz */
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case 620: /* ubfm */
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value = 620; /* --> ubfm. */
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break;
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case 644: /* cset */
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case 643: /* cinc */
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case 642: /* csinc */
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value = 642; /* --> csinc. */
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break;
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case 647: /* csetm */
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case 646: /* cinv */
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case 645: /* csinv */
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value = 645; /* --> csinv. */
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break;
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case 649: /* cneg */
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case 648: /* csneg */
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value = 648; /* --> csneg. */
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break;
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case 667: /* rev */
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case 668: /* rev64 */
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value = 667; /* --> rev. */
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break;
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case 675: /* lsl */
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case 674: /* lslv */
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value = 674; /* --> lslv. */
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break;
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case 677: /* lsr */
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case 676: /* lsrv */
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value = 676; /* --> lsrv. */
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break;
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case 679: /* asr */
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case 678: /* asrv */
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value = 678; /* --> asrv. */
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break;
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case 681: /* ror */
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case 680: /* rorv */
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value = 680; /* --> rorv. */
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break;
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case 691: /* mul */
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case 690: /* madd */
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value = 690; /* --> madd. */
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break;
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case 693: /* mneg */
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case 692: /* msub */
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value = 692; /* --> msub. */
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break;
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case 695: /* smull */
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case 694: /* smaddl */
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value = 694; /* --> smaddl. */
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break;
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case 697: /* smnegl */
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case 696: /* smsubl */
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value = 696; /* --> smsubl. */
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break;
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case 700: /* umull */
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case 699: /* umaddl */
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value = 699; /* --> umaddl. */
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break;
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case 702: /* umnegl */
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case 701: /* umsubl */
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value = 701; /* --> umsubl. */
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break;
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case 713: /* ror */
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case 712: /* extr */
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value = 712; /* --> extr. */
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break;
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case 920: /* bic */
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case 919: /* and */
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value = 919; /* --> and. */
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break;
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case 922: /* mov */
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case 921: /* orr */
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value = 921; /* --> orr. */
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break;
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case 925: /* tst */
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case 924: /* ands */
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value = 924; /* --> ands. */
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break;
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case 930: /* uxtw */
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case 929: /* mov */
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case 928: /* orr */
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value = 928; /* --> orr. */
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break;
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case 932: /* mvn */
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case 931: /* orn */
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value = 931; /* --> orn. */
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break;
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case 936: /* tst */
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case 935: /* ands */
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value = 935; /* --> ands. */
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break;
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case 1062: /* staddb */
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case 966: /* ldaddb */
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value = 966; /* --> ldaddb. */
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break;
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case 1063: /* staddh */
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case 967: /* ldaddh */
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value = 967; /* --> ldaddh. */
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break;
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case 1064: /* stadd */
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case 968: /* ldadd */
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value = 968; /* --> ldadd. */
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2015-11-27 16:25:08 +01:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1065: /* staddlb */
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case 970: /* ldaddlb */
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value = 970; /* --> ldaddlb. */
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2012-08-13 16:52:54 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1066: /* staddlh */
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case 973: /* ldaddlh */
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value = 973; /* --> ldaddlh. */
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2012-08-13 16:52:54 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1067: /* staddl */
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case 976: /* ldaddl */
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value = 976; /* --> ldaddl. */
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2012-08-13 16:52:54 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1068: /* stclrb */
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case 978: /* ldclrb */
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value = 978; /* --> ldclrb. */
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2012-08-13 16:52:54 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1069: /* stclrh */
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case 979: /* ldclrh */
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value = 979; /* --> ldclrh. */
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2012-08-13 16:52:54 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1070: /* stclr */
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case 980: /* ldclr */
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value = 980; /* --> ldclr. */
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2012-08-13 16:52:54 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1071: /* stclrlb */
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case 982: /* ldclrlb */
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value = 982; /* --> ldclrlb. */
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2012-08-13 16:52:54 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1072: /* stclrlh */
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case 985: /* ldclrlh */
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value = 985; /* --> ldclrlh. */
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2012-08-13 16:52:54 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1073: /* stclrl */
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case 988: /* ldclrl */
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value = 988; /* --> ldclrl. */
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include/opcode/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
opcodes/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
* aarch64-asm.c (convert_xtl_to_shll): New function.
(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_xtl_to_shll.
* aarch64-dis.c (convert_shll_to_xtl): New function.
(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_shll_to_xtl.
* aarch64-gen.c: Update copyright year.
* aarch64-asm-2.c: Re-generate.
* aarch64-dis-2.c: Re-generate.
* aarch64-opc-2.c: Re-generate.
gas/testsuite/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/alias.s: Add new tests.
* gas/aarch64/alias.d: Update.
* gas/aarch64/no-aliases.d: Update.
2013-01-30 16:43:32 +01:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1074: /* steorb */
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case 990: /* ldeorb */
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value = 990; /* --> ldeorb. */
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2014-09-03 15:40:41 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1075: /* steorh */
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case 991: /* ldeorh */
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value = 991; /* --> ldeorh. */
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2014-09-03 15:40:41 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1076: /* steor */
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case 992: /* ldeor */
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value = 992; /* --> ldeor. */
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2014-09-03 15:40:41 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1077: /* steorlb */
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case 994: /* ldeorlb */
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value = 994; /* --> ldeorlb. */
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2014-09-03 15:40:41 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1078: /* steorlh */
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case 997: /* ldeorlh */
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value = 997; /* --> ldeorlh. */
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2014-09-03 15:40:41 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1079: /* steorl */
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case 1000: /* ldeorl */
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value = 1000; /* --> ldeorl. */
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2014-09-03 15:40:41 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1080: /* stsetb */
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case 1002: /* ldsetb */
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value = 1002; /* --> ldsetb. */
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2014-09-03 15:40:41 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1081: /* stseth */
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case 1003: /* ldseth */
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value = 1003; /* --> ldseth. */
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2014-09-03 15:40:41 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1082: /* stset */
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case 1004: /* ldset */
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value = 1004; /* --> ldset. */
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2014-09-03 15:40:41 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1083: /* stsetlb */
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case 1006: /* ldsetlb */
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value = 1006; /* --> ldsetlb. */
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2014-09-03 15:40:41 +02:00
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break;
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2015-12-14 18:46:21 +01:00
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case 1084: /* stsetlh */
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|
|
case 1009: /* ldsetlh */
|
|
|
|
value = 1009; /* --> ldsetlh. */
|
2014-09-03 15:40:41 +02:00
|
|
|
break;
|
2015-12-14 18:46:21 +01:00
|
|
|
case 1085: /* stsetl */
|
|
|
|
case 1012: /* ldsetl */
|
|
|
|
value = 1012; /* --> ldsetl. */
|
2014-09-03 15:40:41 +02:00
|
|
|
break;
|
2015-12-14 18:46:21 +01:00
|
|
|
case 1086: /* stsmaxb */
|
|
|
|
case 1014: /* ldsmaxb */
|
|
|
|
value = 1014; /* --> ldsmaxb. */
|
2014-09-03 15:40:41 +02:00
|
|
|
break;
|
2015-12-14 18:46:21 +01:00
|
|
|
case 1087: /* stsmaxh */
|
|
|
|
case 1015: /* ldsmaxh */
|
|
|
|
value = 1015; /* --> ldsmaxh. */
|
2014-09-03 15:40:41 +02:00
|
|
|
break;
|
2015-12-14 18:46:21 +01:00
|
|
|
case 1088: /* stsmax */
|
|
|
|
case 1016: /* ldsmax */
|
|
|
|
value = 1016; /* --> ldsmax. */
|
|
|
|
break;
|
|
|
|
case 1089: /* stsmaxlb */
|
|
|
|
case 1018: /* ldsmaxlb */
|
|
|
|
value = 1018; /* --> ldsmaxlb. */
|
|
|
|
break;
|
|
|
|
case 1090: /* stsmaxlh */
|
|
|
|
case 1021: /* ldsmaxlh */
|
|
|
|
value = 1021; /* --> ldsmaxlh. */
|
|
|
|
break;
|
|
|
|
case 1091: /* stsmaxl */
|
|
|
|
case 1024: /* ldsmaxl */
|
|
|
|
value = 1024; /* --> ldsmaxl. */
|
|
|
|
break;
|
|
|
|
case 1092: /* stsminb */
|
|
|
|
case 1026: /* ldsminb */
|
|
|
|
value = 1026; /* --> ldsminb. */
|
|
|
|
break;
|
|
|
|
case 1093: /* stsminh */
|
|
|
|
case 1027: /* ldsminh */
|
|
|
|
value = 1027; /* --> ldsminh. */
|
|
|
|
break;
|
|
|
|
case 1094: /* stsmin */
|
|
|
|
case 1028: /* ldsmin */
|
|
|
|
value = 1028; /* --> ldsmin. */
|
|
|
|
break;
|
|
|
|
case 1095: /* stsminlb */
|
|
|
|
case 1030: /* ldsminlb */
|
|
|
|
value = 1030; /* --> ldsminlb. */
|
|
|
|
break;
|
|
|
|
case 1096: /* stsminlh */
|
|
|
|
case 1033: /* ldsminlh */
|
|
|
|
value = 1033; /* --> ldsminlh. */
|
|
|
|
break;
|
|
|
|
case 1097: /* stsminl */
|
|
|
|
case 1036: /* ldsminl */
|
|
|
|
value = 1036; /* --> ldsminl. */
|
|
|
|
break;
|
|
|
|
case 1098: /* stumaxb */
|
|
|
|
case 1038: /* ldumaxb */
|
|
|
|
value = 1038; /* --> ldumaxb. */
|
|
|
|
break;
|
|
|
|
case 1099: /* stumaxh */
|
|
|
|
case 1039: /* ldumaxh */
|
|
|
|
value = 1039; /* --> ldumaxh. */
|
|
|
|
break;
|
|
|
|
case 1100: /* stumax */
|
|
|
|
case 1040: /* ldumax */
|
|
|
|
value = 1040; /* --> ldumax. */
|
|
|
|
break;
|
|
|
|
case 1101: /* stumaxlb */
|
|
|
|
case 1042: /* ldumaxlb */
|
|
|
|
value = 1042; /* --> ldumaxlb. */
|
|
|
|
break;
|
|
|
|
case 1102: /* stumaxlh */
|
|
|
|
case 1045: /* ldumaxlh */
|
|
|
|
value = 1045; /* --> ldumaxlh. */
|
|
|
|
break;
|
|
|
|
case 1103: /* stumaxl */
|
|
|
|
case 1048: /* ldumaxl */
|
|
|
|
value = 1048; /* --> ldumaxl. */
|
|
|
|
break;
|
|
|
|
case 1104: /* stuminb */
|
|
|
|
case 1050: /* lduminb */
|
|
|
|
value = 1050; /* --> lduminb. */
|
|
|
|
break;
|
|
|
|
case 1105: /* stuminh */
|
|
|
|
case 1051: /* lduminh */
|
|
|
|
value = 1051; /* --> lduminh. */
|
|
|
|
break;
|
|
|
|
case 1106: /* stumin */
|
|
|
|
case 1052: /* ldumin */
|
|
|
|
value = 1052; /* --> ldumin. */
|
|
|
|
break;
|
|
|
|
case 1107: /* stuminlb */
|
|
|
|
case 1054: /* lduminlb */
|
|
|
|
value = 1054; /* --> lduminlb. */
|
|
|
|
break;
|
|
|
|
case 1108: /* stuminlh */
|
|
|
|
case 1057: /* lduminlh */
|
|
|
|
value = 1057; /* --> lduminlh. */
|
|
|
|
break;
|
|
|
|
case 1109: /* stuminl */
|
|
|
|
case 1060: /* lduminl */
|
|
|
|
value = 1060; /* --> lduminl. */
|
|
|
|
break;
|
|
|
|
case 1111: /* mov */
|
|
|
|
case 1110: /* movn */
|
|
|
|
value = 1110; /* --> movn. */
|
|
|
|
break;
|
|
|
|
case 1113: /* mov */
|
|
|
|
case 1112: /* movz */
|
|
|
|
value = 1112; /* --> movz. */
|
|
|
|
break;
|
|
|
|
case 1126: /* psb */
|
|
|
|
case 1125: /* esb */
|
|
|
|
case 1124: /* sevl */
|
|
|
|
case 1123: /* sev */
|
|
|
|
case 1122: /* wfi */
|
|
|
|
case 1121: /* wfe */
|
|
|
|
case 1120: /* yield */
|
|
|
|
case 1119: /* nop */
|
|
|
|
case 1118: /* hint */
|
|
|
|
value = 1118; /* --> hint. */
|
|
|
|
break;
|
|
|
|
case 1135: /* tlbi */
|
|
|
|
case 1134: /* ic */
|
|
|
|
case 1133: /* dc */
|
|
|
|
case 1132: /* at */
|
|
|
|
case 1131: /* sys */
|
|
|
|
value = 1131; /* --> sys. */
|
2012-08-13 16:52:54 +02:00
|
|
|
break;
|
|
|
|
default: return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return aarch64_opcode_table + value;
|
|
|
|
}
|
|
|
|
|
|
|
|
const char*
|
|
|
|
aarch64_insert_operand (const aarch64_operand *self,
|
|
|
|
const aarch64_opnd_info *info,
|
|
|
|
aarch64_insn *code, const aarch64_inst *inst)
|
|
|
|
{
|
|
|
|
/* Use the index as the key. */
|
|
|
|
int key = self - aarch64_operands;
|
|
|
|
switch (key)
|
|
|
|
{
|
|
|
|
case 1:
|
|
|
|
case 2:
|
|
|
|
case 3:
|
|
|
|
case 4:
|
|
|
|
case 5:
|
|
|
|
case 6:
|
|
|
|
case 7:
|
|
|
|
case 8:
|
|
|
|
case 9:
|
|
|
|
case 10:
|
|
|
|
case 14:
|
|
|
|
case 15:
|
|
|
|
case 16:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 17:
|
2012-08-13 16:52:54 +02:00
|
|
|
case 19:
|
|
|
|
case 20:
|
|
|
|
case 21:
|
|
|
|
case 22:
|
|
|
|
case 23:
|
|
|
|
case 24:
|
|
|
|
case 25:
|
|
|
|
case 26:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 27:
|
2012-08-13 16:52:54 +02:00
|
|
|
case 35:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 36:
|
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 17:55:49 +02:00
|
|
|
case 123:
|
|
|
|
case 124:
|
|
|
|
case 125:
|
|
|
|
case 126:
|
|
|
|
case 127:
|
|
|
|
case 128:
|
|
|
|
case 129:
|
|
|
|
case 130:
|
|
|
|
case 131:
|
|
|
|
case 132:
|
|
|
|
case 133:
|
|
|
|
case 134:
|
|
|
|
case 135:
|
|
|
|
case 136:
|
|
|
|
case 139:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ins_regno (self, info, code, inst);
|
|
|
|
case 12:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_reg_extended (self, info, code, inst);
|
|
|
|
case 13:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ins_reg_shifted (self, info, code, inst);
|
2014-09-03 15:40:41 +02:00
|
|
|
case 18:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ins_ft (self, info, code, inst);
|
|
|
|
case 28:
|
|
|
|
case 29:
|
|
|
|
case 30:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_reglane (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 31:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_reglist (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 32:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_ldst_reglist (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 33:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_ldst_reglist_r (self, info, code, inst);
|
|
|
|
case 34:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ins_ldst_elemlist (self, info, code, inst);
|
2014-09-03 15:40:41 +02:00
|
|
|
case 37:
|
2012-08-13 16:52:54 +02:00
|
|
|
case 47:
|
|
|
|
case 48:
|
|
|
|
case 49:
|
|
|
|
case 50:
|
|
|
|
case 51:
|
|
|
|
case 52:
|
|
|
|
case 53:
|
|
|
|
case 54:
|
|
|
|
case 55:
|
|
|
|
case 56:
|
|
|
|
case 57:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 58:
|
2012-08-13 16:52:54 +02:00
|
|
|
case 67:
|
|
|
|
case 68:
|
2013-11-05 21:50:18 +01:00
|
|
|
case 69:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 70:
|
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 17:55:49 +02:00
|
|
|
case 120:
|
|
|
|
case 122:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ins_imm (self, info, code, inst);
|
|
|
|
case 38:
|
|
|
|
case 39:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_advsimd_imm_shift (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 40:
|
|
|
|
case 41:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 42:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
|
2016-09-21 17:51:24 +02:00
|
|
|
case 46:
|
|
|
|
return aarch64_ins_fpimm (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 59:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_limm (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 60:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_aimm (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 61:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_imm_half (self, info, code, inst);
|
|
|
|
case 62:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ins_fbits (self, info, code, inst);
|
2013-11-05 21:50:18 +01:00
|
|
|
case 64:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 65:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ins_cond (self, info, code, inst);
|
|
|
|
case 71:
|
2014-09-03 15:40:41 +02:00
|
|
|
case 77:
|
|
|
|
return aarch64_ins_addr_simple (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 72:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_addr_regoff (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 73:
|
|
|
|
case 74:
|
2013-11-05 21:50:18 +01:00
|
|
|
case 75:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_addr_simm (self, info, code, inst);
|
|
|
|
case 76:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ins_addr_uimm12 (self, info, code, inst);
|
|
|
|
case 78:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_simd_addr_post (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 79:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_sysreg (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 80:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_pstatefield (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 81:
|
|
|
|
case 82:
|
|
|
|
case 83:
|
|
|
|
case 84:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_sysins_op (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
|
case 85:
|
2013-11-05 21:50:18 +01:00
|
|
|
case 86:
|
2014-09-03 15:40:41 +02:00
|
|
|
return aarch64_ins_barrier (self, info, code, inst);
|
|
|
|
case 87:
|
2012-08-13 16:52:54 +02:00
|
|
|
return aarch64_ins_prfop (self, info, code, inst);
|
2015-12-11 11:22:40 +01:00
|
|
|
case 88:
|
|
|
|
return aarch64_ins_hint (self, info, code, inst);
|
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 17:55:49 +02:00
|
|
|
case 89:
|
[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:
UQINCD X0, POW2, MUL #2
This patch adds support for this kind of operand.
All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context. This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).
In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code. I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
aarch64_opnd.
(AARCH64_MOD_MUL): New aarch64_modifier_kind.
(aarch64_opnd_info): Make shifter.amount an int64_t and
rearrange the fields.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
* aarch64-opc.c (fields): Add a corresponding entry.
(set_multiplier_out_of_range_error): New function.
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
(operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
(print_register_offset_address): Use PRIi64 to print the
shift amount.
(aarch64_print_operand): Likewise. Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_scale): New inserter.
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_scale): New inserter.
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
shift modes. Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.
2016-09-21 17:55:22 +02:00
|
|
|
case 90:
|
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 17:55:49 +02:00
|
|
|
case 91:
|
|
|
|
case 92:
|
|
|
|
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
|
|
|
|
case 93:
|
|
|
|
case 94:
|
|
|
|
case 95:
|
|
|
|
case 96:
|
|
|
|
case 97:
|
|
|
|
case 98:
|
|
|
|
case 99:
|
|
|
|
case 100:
|
|
|
|
case 101:
|
|
|
|
case 102:
|
|
|
|
case 103:
|
|
|
|
case 104:
|
|
|
|
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
|
|
|
|
case 105:
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 17:53:54 +02:00
|
|
|
case 106:
|
[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:
UQINCD X0, POW2, MUL #2
This patch adds support for this kind of operand.
All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context. This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).
In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code. I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
aarch64_opnd.
(AARCH64_MOD_MUL): New aarch64_modifier_kind.
(aarch64_opnd_info): Make shifter.amount an int64_t and
rearrange the fields.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
* aarch64-opc.c (fields): Add a corresponding entry.
(set_multiplier_out_of_range_error): New function.
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
(operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
(print_register_offset_address): Use PRIi64 to print the
shift amount.
(aarch64_print_operand): Likewise. Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_scale): New inserter.
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_scale): New inserter.
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
shift modes. Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.
2016-09-21 17:55:22 +02:00
|
|
|
case 107:
|
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 17:55:49 +02:00
|
|
|
case 108:
|
[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:
UQINCD X0, POW2, MUL #2
This patch adds support for this kind of operand.
All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context. This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).
In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code. I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
aarch64_opnd.
(AARCH64_MOD_MUL): New aarch64_modifier_kind.
(aarch64_opnd_info): Make shifter.amount an int64_t and
rearrange the fields.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
* aarch64-opc.c (fields): Add a corresponding entry.
(set_multiplier_out_of_range_error): New function.
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
(operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
(print_register_offset_address): Use PRIi64 to print the
shift amount.
(aarch64_print_operand): Likewise. Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_scale): New inserter.
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_scale): New inserter.
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other
shift modes. Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.
2016-09-21 17:55:22 +02:00
|
|
|
case 109:
|
[AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands. A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.
The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64. Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters. Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.
2016-09-21 17:55:49 +02:00
|
|
|
case 110:
|
|
|
|
case 111:
|
|
|
|
case 112:
|
|
|
|
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
|
|
|
|
case 113:
|
|
|
|
case 114:
|
|
|
|
case 115:
|
|
|
|
case 116:
|
|
|
|
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
|
|
|
|
case 117:
|
|
|
|
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
|
|
|
|
case 118:
|
|
|
|
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
|
|
|
|
case 119:
|
|
|
|
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
|
|
|
|
case 121:
|
|
|
|
return aarch64_ins_sve_scale (self, info, code, inst);
|
|
|
|
case 137:
|
|
|
|
return aarch64_ins_sve_index (self, info, code, inst);
|
|
|
|
case 138:
|
|
|
|
case 140:
|
[AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
2016-09-21 17:53:54 +02:00
|
|
|
return aarch64_ins_sve_reglist (self, info, code, inst);
|
2012-08-13 16:52:54 +02:00
|
|
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default: assert (0); abort ();
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}
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}
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