2018-01-03 06:17:27 +01:00
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@c Copyright (C) 2000-2018 Free Software Foundation, Inc.
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2001-01-12 18:50:59 +01:00
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node ARC-Dependent
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@chapter ARC Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter ARC Dependent Features
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@end ifclear
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2001-05-12 17:14:53 +02:00
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@set ARC_CORE_DEFAULT 6
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2001-01-12 18:50:59 +01:00
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@cindex ARC support
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@menu
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* ARC Options:: Options
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* ARC Syntax:: Syntax
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* ARC Directives:: ARC Machine Directives
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2015-10-07 15:20:19 +02:00
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* ARC Modifiers:: ARC Assembler Modifiers
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* ARC Symbols:: ARC Pre-defined Symbols
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2001-01-12 18:50:59 +01:00
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* ARC Opcodes:: Opcodes
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@end menu
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@node ARC Options
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@section Options
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2015-10-07 15:20:19 +02:00
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@cindex ARC options
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@cindex options for ARC
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The following options control the type of CPU for which code is
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assembled, and generic constraints on the code generated:
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2001-01-12 18:50:59 +01:00
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@table @code
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2015-10-07 15:20:19 +02:00
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@item -mcpu=@var{cpu}
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@cindex @code{-mcpu=@var{cpu}} command line option, ARC
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Set architecture type and register usage for @var{cpu}. There are
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also shortcut alias options available for backward compatibility and
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convenience. Supported values for @var{cpu} are
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2001-01-12 18:50:59 +01:00
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@table @code
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2015-10-07 15:20:19 +02:00
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@cindex @code{mA6} command line option, ARC
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@cindex @code{marc600} command line option, ARC
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@item arc600
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Assemble for ARC 600. Aliases: @code{-mA6}, @code{-mARC600}.
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2001-01-12 18:50:59 +01:00
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2016-12-02 16:08:10 +01:00
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@item arc600_norm
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Assemble for ARC 600 with norm instructions.
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@item arc600_mul64
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Assemble for ARC 600 with mul64 instructions.
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@item arc600_mul32x16
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Assemble for ARC 600 with mul32x16 instructions.
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2015-10-07 15:20:19 +02:00
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@item arc601
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@cindex @code{mARC601} command line option, ARC
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Assemble for ARC 601. Alias: @code{-mARC601}.
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2001-01-12 18:50:59 +01:00
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2016-12-02 16:08:10 +01:00
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@item arc601_norm
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Assemble for ARC 601 with norm instructions.
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@item arc601_mul64
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Assemble for ARC 601 with mul64 instructions.
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@item arc601_mul32x16
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Assemble for ARC 601 with mul32x16 instructions.
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2015-10-07 15:20:19 +02:00
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@item arc700
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@cindex @code{mA7} command line option, ARC
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@cindex @code{mARC700} command line option, ARC
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Assemble for ARC 700. Aliases: @code{-mA7}, @code{-mARC700}.
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2001-01-12 18:50:59 +01:00
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2015-10-07 15:20:19 +02:00
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@item arcem
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@cindex @code{mEM} command line option, ARC
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Assemble for ARC EM. Aliases: @code{-mEM}
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2016-12-02 16:08:10 +01:00
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@item em
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Assemble for ARC EM, identical as arcem variant.
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@item em4
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Assemble for ARC EM with code-density instructions.
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@item em4_dmips
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Assemble for ARC EM with code-density instructions.
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@item em4_fpus
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Assemble for ARC EM with code-density instructions.
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@item em4_fpuda
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Assemble for ARC EM with code-density, and double-precision assist
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instructions.
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@item quarkse_em
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Assemble for QuarkSE-EM cpu.
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2015-10-07 15:20:19 +02:00
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@item archs
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@cindex @code{mHS} command line option, ARC
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Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}.
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2001-01-12 18:50:59 +01:00
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2016-12-02 16:08:10 +01:00
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@item hs
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Assemble for ARC HS.
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@item hs34
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Assemble for ARC HS34.
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@item hs38
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Assemble for ARC HS38.
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@item hs38_linux
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Assemble for ARC HS38 with floating point support on.
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2016-06-21 15:03:08 +02:00
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@item nps400
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@cindex @code{mnps400} command line option, ARC
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Assemble for ARC 700 with NPS-400 extended instructions.
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2001-01-12 18:50:59 +01:00
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@end table
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2016-04-19 20:02:27 +02:00
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Note: the @code{.cpu} directive (@pxref{ARC Directives}) can
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to be used to select a core variant from within assembly code.
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2001-01-12 18:50:59 +01:00
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@cindex @code{-EB} command line option, ARC
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@item -EB
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a big-endian processor.
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@cindex @code{-EL} command line option, ARC
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@item -EL
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a little-endian processor - this is the
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default.
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2015-10-07 15:20:19 +02:00
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@cindex @code{-mcode-density} command line option, ARC
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@item -mcode-density
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This option turns on Code Density instructions. Only valid for ARC EM
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processors.
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Add support for ARC instruction relaxation in the assembler.
gas/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
Define.
(arc_flags, arc_relax_type): New structure.
* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
(RELAX_TABLE_ENTRY_MAX): New define.
(relaxation_state, md_relax_table, arc_relaxable_insns)
(arc_num_relaxable_ins): New variable.
(rlx_operand_type, arc_rlx_types): New enums.
(arc_relaxable_ins): New structure.
(OPTION_RELAX): New option.
(arc_insn): New relax member.
(arc_flags): Remove.
(relax_insn_p): New function.
(apply_fixups): Likewise.
(relaxable_operand): Likewise.
(may_relax_expr): Likewise.
(relaxable_flag): Likewise.
(arc_pcrel_adjust): Likewise.
(md_estimate_size_before_relax): Implement.
(md_convert_frag): Likewise.
(md_parse_option): Handle new mrelax option.
(md_show_usage): Likewise.
(assemble_insn): Set relax member.
(emit_insn0): New function.
(emit_insn1): Likewise.
(emit_insn): Handle relaxation case.
* NEWS: Mention the new relaxation option.
* doc/c-arc.texi (ARC Options): Document new mrelax option.
gas/testsuite
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
* gas/arc/relax-avoid1.d: New file.
* gas/arc/relax-avoid1.s: Likewise.
* gas/arc/relax-avoid2.d: Likewise.
* gas/arc/relax-avoid2.s: Likewise.
* gas/arc/relax-avoid3.d: Likewise.
* gas/arc/relax-avoid3.s: Likewise.
* gas/arc/relax-b.d: Likewise.
* gas/arc/relax-b.s: Likewise.
include/opcode/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
Declare.
opcodes/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
variable.
2016-02-10 13:09:01 +01:00
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@cindex @code{-mrelax} command line option, ARC
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@item -mrelax
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Enable support for assembly-time relaxation. The assembler will
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replace a longer version of an instruction with a shorter one,
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whenever it is possible.
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2016-06-21 15:03:08 +02:00
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@cindex @code{-mnps400} command line option, ARC
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@item -mnps400
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Enable support for NPS-400 extended instructions.
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@cindex @code{-mspfp} command line option, ARC
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@item -mspfp
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Enable support for single-precision floating point instructions.
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@cindex @code{-mdpfp} command line option, ARC
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@item -mdpfp
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Enable support for double-precision floating point instructions.
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@cindex @code{-mfpuda} command line option, ARC
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@item -mfpuda
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Enable support for double-precision assist floating point instructions.
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Only valid for ARC EM processors.
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2001-01-12 18:50:59 +01:00
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@end table
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@node ARC Syntax
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@section Syntax
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@menu
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* ARC-Chars:: Special Characters
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* ARC-Regs:: Register Names
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@end menu
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@node ARC-Chars
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@subsection Special Characters
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2015-10-07 15:20:19 +02:00
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@table @code
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@item %
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@cindex register name prefix character, ARC
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@cindex ARC register name prefix character
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A register name can optionally be prefixed by a @samp{%} character. So
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register @code{%r0} is equivalent to @code{r0} in the assembly code.
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@item #
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2011-01-18 14:37:39 +01:00
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@cindex line comment character, ARC
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@cindex ARC line comment character
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2015-10-07 15:20:19 +02:00
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The presence of a @samp{#} character within a line (but not at the
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start of a line) indicates the start of a comment that extends to the
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end of the current line.
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@emph{Note:} if a line starts with a @samp{#} character then it can
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also be a logical line number directive (@pxref{Comments}) or a
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preprocessor control command (@pxref{Preprocessing}).
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@item @@
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@cindex symbol prefix character, ARC
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@cindex ARC symbol prefix character
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Prefixing an operand with an @samp{@@} specifies that the operand is a
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symbol and not a register. This is how the assembler disambiguates
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the use of an ARC register name as a symbol. So the instruction
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@example
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mov r0, @@r0
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@end example
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moves the address of symbol @code{r0} into register @code{r0}.
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@item `
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2011-01-18 14:37:39 +01:00
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@cindex line separator, ARC
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@cindex statement separator, ARC
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@cindex ARC line separator
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2015-10-07 15:20:19 +02:00
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The @samp{`} (backtick) character is used to separate statements on a
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single line.
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@cindex line
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@item -
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@cindex C preprocessor macro separator, ARC
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@cindex ARC C preprocessor macro separator
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Used as a separator to obtain a sequence of commands from a C
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preprocessor macro.
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@end table
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2001-01-12 18:50:59 +01:00
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@node ARC-Regs
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@subsection Register Names
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@cindex ARC register names
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@cindex register names, ARC
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2015-10-07 15:20:19 +02:00
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The ARC assembler uses the following register names for its core
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registers:
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@table @code
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@item r0-r31
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@cindex core general registers, ARC
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@cindex ARC core general registers
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The core general registers. Registers @code{r26} through @code{r31}
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have special functions, and are usually referred to by those synonyms.
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@item gp
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@cindex global pointer, ARC
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@cindex ARC global pointer
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The global pointer and a synonym for @code{r26}.
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@item fp
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@cindex frame pointer, ARC
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@cindex ARC frame pointer
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The frame pointer and a synonym for @code{r27}.
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@item sp
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@cindex stack pointer, ARC
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@cindex ARC stack pointer
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The stack pointer and a synonym for @code{r28}.
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@item ilink1
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@cindex level 1 interrupt link register, ARC
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@cindex ARC level 1 interrupt link register
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For ARC 600 and ARC 700, the level 1 interrupt link register and a
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synonym for @code{r29}. Not supported for ARCv2.
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@item ilink
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@cindex interrupt link register, ARC
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@cindex ARC interrupt link register
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For ARCv2, the interrupt link register and a synonym for @code{r29}.
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Not supported for ARC 600 and ARC 700.
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@item ilink2
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@cindex level 2 interrupt link register, ARC
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@cindex ARC level 2 interrupt link register
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For ARC 600 and ARC 700, the level 2 interrupt link register and a
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synonym for @code{r30}. Not supported for ARC v2.
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@item blink
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@cindex link register, ARC
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@cindex ARC link register
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The link register and a synonym for @code{r31}.
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@item r32-r59
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@cindex extension core registers, ARC
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@cindex ARC extension core registers
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The extension core registers.
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@item lp_count
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@cindex loop counter, ARC
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@cindex ARC loop counter
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The loop count register.
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@item pcl
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@cindex word aligned program counter, ARC
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@cindex ARC word aligned program counter
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The word aligned program counter.
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@end table
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2001-01-12 18:50:59 +01:00
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2015-10-07 15:20:19 +02:00
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In addition the ARC processor has a large number of @emph{auxiliary
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registers}. The precise set depends on the extensions being
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supported, but the following baseline set are always defined:
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2001-01-12 18:50:59 +01:00
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2015-10-07 15:20:19 +02:00
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@table @code
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@item identity
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@cindex Processor Identification register, ARC
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@cindex ARC Processor Identification register
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Processor Identification register. Auxiliary register address 0x4.
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@item pc
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@cindex Program Counter, ARC
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@cindex ARC Program Counter
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Program Counter. Auxiliary register address 0x6.
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@item status32
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@cindex Status register, ARC
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@cindex ARC Status register
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Status register. Auxiliary register address 0x0a.
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@item bta
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@cindex Branch Target Address, ARC
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@cindex ARC Branch Target Address
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Branch Target Address. Auxiliary register address 0x412.
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@item ecr
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@cindex Exception Cause Register, ARC
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@cindex ARC Exception Cause Register
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Exception Cause Register. Auxiliary register address 0x403.
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@item int_vector_base
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@cindex Interrupt Vector Base address, ARC
|
|
|
|
@cindex ARC Interrupt Vector Base address
|
|
|
|
Interrupt Vector Base address. Auxiliary register address 0x25.
|
|
|
|
|
|
|
|
@item status32_p0
|
|
|
|
@cindex Stored STATUS32 register on entry to level P0 interrupts, ARC
|
|
|
|
@cindex ARC Stored STATUS32 register on entry to level P0 interrupts
|
|
|
|
Stored STATUS32 register on entry to level P0 interrupts. Auxiliary
|
|
|
|
register address 0xb.
|
|
|
|
|
|
|
|
@item aux_user_sp
|
|
|
|
@cindex Saved User Stack Pointer, ARC
|
|
|
|
@cindex ARC Saved User Stack Pointer
|
|
|
|
Saved User Stack Pointer. Auxiliary register address 0xd.
|
|
|
|
|
|
|
|
@item eret
|
|
|
|
@cindex Exception Return Address, ARC
|
|
|
|
@cindex ARC Exception Return Address
|
|
|
|
Exception Return Address. Auxiliary register address 0x400.
|
|
|
|
|
|
|
|
@item erbta
|
|
|
|
@cindex BTA saved on exception entry, ARC
|
|
|
|
@cindex ARC BTA saved on exception entry
|
|
|
|
BTA saved on exception entry. Auxiliary register address 0x401.
|
|
|
|
|
|
|
|
@item erstatus
|
|
|
|
@cindex STATUS32 saved on exception, ARC
|
|
|
|
@cindex ARC STATUS32 saved on exception
|
|
|
|
STATUS32 saved on exception. Auxiliary register address 0x402.
|
|
|
|
|
|
|
|
@item bcr_ver
|
|
|
|
@cindex Build Configuration Registers Version, ARC
|
|
|
|
@cindex ARC Build Configuration Registers Version
|
|
|
|
Build Configuration Registers Version. Auxiliary register address 0x60.
|
|
|
|
|
|
|
|
@item bta_link_build
|
|
|
|
@cindex Build configuration for: BTA Registers, ARC
|
|
|
|
@cindex ARC Build configuration for: BTA Registers
|
|
|
|
Build configuration for: BTA Registers. Auxiliary register address 0x63.
|
|
|
|
|
|
|
|
@item vecbase_ac_build
|
|
|
|
@cindex Build configuration for: Interrupts, ARC
|
|
|
|
@cindex ARC Build configuration for: Interrupts
|
|
|
|
Build configuration for: Interrupts. Auxiliary register address 0x68.
|
|
|
|
|
|
|
|
@item rf_build
|
|
|
|
@cindex Build configuration for: Core Registers, ARC
|
|
|
|
@cindex ARC Build configuration for: Core Registers
|
|
|
|
Build configuration for: Core Registers. Auxiliary register address 0x6e.
|
|
|
|
|
|
|
|
@item dccm_build
|
|
|
|
@cindex DCCM RAM Configuration Register, ARC
|
|
|
|
@cindex ARC DCCM RAM Configuration Register
|
|
|
|
DCCM RAM Configuration Register. Auxiliary register address 0xc1.
|
2001-01-12 18:50:59 +01:00
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
@end table
|
2001-01-12 18:50:59 +01:00
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
Additional auxiliary register names are defined according to the
|
|
|
|
processor architecture version and extensions selected by the options.
|
2001-01-12 18:50:59 +01:00
|
|
|
|
|
|
|
@node ARC Directives
|
|
|
|
@section ARC Machine Directives
|
|
|
|
|
|
|
|
@cindex machine directives, ARC
|
|
|
|
@cindex ARC machine directives
|
|
|
|
The ARC version of @code{@value{AS}} supports the following additional
|
|
|
|
machine directives:
|
|
|
|
|
|
|
|
@table @code
|
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
@cindex @code{lcomm} directive
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
|
@item .lcomm @var{symbol}, @var{length}[, @var{alignment}]
|
2015-10-07 15:20:19 +02:00
|
|
|
Reserve @var{length} (an absolute expression) bytes for a local common
|
|
|
|
denoted by @var{symbol}. The section and value of @var{symbol} are
|
|
|
|
those of the new local common. The addresses are allocated in the bss
|
|
|
|
section, so that at run-time the bytes start off zeroed. Since
|
|
|
|
@var{symbol} is not declared global, it is normally not visible to
|
|
|
|
@code{@value{LD}}. The optional third parameter, @var{alignment},
|
|
|
|
specifies the desired alignment of the symbol in the bss section,
|
|
|
|
specified as a byte boundary (for example, an alignment of 16 means
|
|
|
|
that the least significant 4 bits of the address should be zero). The
|
|
|
|
alignment must be an absolute expression, and it must be a power of
|
|
|
|
two. If no alignment is specified, as will set the alignment to the
|
|
|
|
largest power of two less than or equal to the size of the symbol, up
|
|
|
|
to a maximum of 16.
|
|
|
|
|
2016-04-06 16:08:04 +02:00
|
|
|
@cindex @code{lcommon} directive, ARC
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
|
@item .lcommon @var{symbol}, @var{length}[, @var{alignment}]
|
2015-10-07 15:20:19 +02:00
|
|
|
The same as @code{lcomm} directive.
|
|
|
|
|
2016-04-06 16:08:04 +02:00
|
|
|
@cindex @code{cpu} directive, ARC
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
|
@item .cpu @var{cpu}
|
2015-10-07 15:20:19 +02:00
|
|
|
The @code{.cpu} directive must be followed by the desired core
|
|
|
|
version. Permitted values for CPU are:
|
2005-02-28 19:05:06 +01:00
|
|
|
@table @code
|
2015-10-07 15:20:19 +02:00
|
|
|
@item ARC600
|
|
|
|
Assemble for the ARC600 instruction set.
|
2001-01-12 18:50:59 +01:00
|
|
|
|
2016-12-02 16:08:10 +01:00
|
|
|
@item arc600_norm
|
|
|
|
Assemble for ARC 600 with norm instructions.
|
|
|
|
|
|
|
|
@item arc600_mul64
|
|
|
|
Assemble for ARC 600 with mul64 instructions.
|
|
|
|
|
|
|
|
@item arc600_mul32x16
|
|
|
|
Assemble for ARC 600 with mul32x16 instructions.
|
|
|
|
|
|
|
|
@item arc601
|
|
|
|
Assemble for ARC 601 instruction set.
|
|
|
|
|
|
|
|
@item arc601_norm
|
|
|
|
Assemble for ARC 601 with norm instructions.
|
|
|
|
|
|
|
|
@item arc601_mul64
|
|
|
|
Assemble for ARC 601 with mul64 instructions.
|
|
|
|
|
|
|
|
@item arc601_mul32x16
|
|
|
|
Assemble for ARC 601 with mul32x16 instructions.
|
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
@item ARC700
|
|
|
|
Assemble for the ARC700 instruction set.
|
2005-02-28 19:05:06 +01:00
|
|
|
|
2016-04-19 20:02:27 +02:00
|
|
|
@item NPS400
|
|
|
|
Assemble for the NPS400 instruction set.
|
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
@item EM
|
|
|
|
Assemble for the ARC EM instruction set.
|
2001-01-12 18:50:59 +01:00
|
|
|
|
2016-12-02 16:08:10 +01:00
|
|
|
@item arcem
|
|
|
|
Assemble for ARC EM instruction set
|
|
|
|
|
|
|
|
@item em4
|
|
|
|
Assemble for ARC EM with code-density instructions.
|
|
|
|
|
|
|
|
@item em4_dmips
|
|
|
|
Assemble for ARC EM with code-density instructions.
|
|
|
|
|
|
|
|
@item em4_fpus
|
|
|
|
Assemble for ARC EM with code-density instructions.
|
|
|
|
|
|
|
|
@item em4_fpuda
|
|
|
|
Assemble for ARC EM with code-density, and double-precision assist
|
|
|
|
instructions.
|
|
|
|
|
|
|
|
@item quarkse_em
|
|
|
|
Assemble for QuarkSE-EM instruction set.
|
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
@item HS
|
|
|
|
Assemble for the ARC HS instruction set.
|
2013-01-10 20:51:55 +01:00
|
|
|
|
2016-12-02 16:08:10 +01:00
|
|
|
@item archs
|
|
|
|
Assemble for ARC HS instruction set.
|
|
|
|
|
|
|
|
@item hs
|
|
|
|
Assemble for ARC HS instruction set.
|
|
|
|
|
|
|
|
@item hs34
|
|
|
|
Assemble for ARC HS34 instruction set.
|
|
|
|
|
|
|
|
@item hs38
|
|
|
|
Assemble for ARC HS38 instruction set.
|
|
|
|
|
|
|
|
@item hs38_linux
|
|
|
|
Assemble for ARC HS38 with floating point support on.
|
|
|
|
|
2005-02-28 19:05:06 +01:00
|
|
|
@end table
|
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
Note: the @code{.cpu} directive overrides the command line option
|
|
|
|
@code{-mcpu=@var{cpu}}; a warning is emitted when the version is not
|
|
|
|
consistent between the two.
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
|
|
2016-04-06 16:08:04 +02:00
|
|
|
@item .extAuxRegister @var{name}, @var{addr}, @var{mode}
|
|
|
|
@cindex @code{extAuxRegister} directive, ARC
|
|
|
|
Auxiliary registers can be defined in the assembler source code by
|
|
|
|
using this directive. The first parameter, @var{name}, is the name of the
|
|
|
|
new auxiliary register. The second parameter, @var{addr}, is
|
|
|
|
address the of the auxiliary register. The third parameter,
|
|
|
|
@var{mode}, specifies whether the register is readable and/or writable
|
|
|
|
and is one of:
|
|
|
|
@table @code
|
|
|
|
@item r
|
|
|
|
Read only;
|
|
|
|
|
|
|
|
@item w
|
|
|
|
Write only;
|
|
|
|
|
|
|
|
@item r|w
|
|
|
|
Read and write.
|
|
|
|
|
|
|
|
@end table
|
|
|
|
|
|
|
|
For example:
|
|
|
|
@example
|
|
|
|
.extAuxRegister mulhi, 0x12, w
|
|
|
|
@end example
|
|
|
|
specifies a write only extension auxiliary register, @var{mulhi} at
|
|
|
|
address 0x12.
|
|
|
|
|
|
|
|
@item .extCondCode @var{suffix}, @var{val}
|
|
|
|
@cindex @code{extCondCode} directive, ARC
|
|
|
|
ARC supports extensible condition codes. This directive defines a new
|
|
|
|
condition code, to be known by the suffix, @var{suffix} and will
|
|
|
|
depend on the value, @var{val} in the condition code.
|
|
|
|
|
|
|
|
For example:
|
|
|
|
@example
|
|
|
|
.extCondCode is_busy,0x14
|
|
|
|
add.is_busy r1,r2,r3
|
|
|
|
@end example
|
|
|
|
will only execute the @code{add} instruction if the condition code
|
|
|
|
value is 0x14.
|
|
|
|
|
|
|
|
@item .extCoreRegister @var{name}, @var{regnum}, @var{mode}, @var{shortcut}
|
|
|
|
@cindex @code{extCoreRegister} directive, ARC
|
|
|
|
Specifies an extension core register named @var{name} as a synonym for
|
|
|
|
the register numbered @var{regnum}. The register number must be
|
|
|
|
between 32 and 59. The third argument, @var{mode}, indicates whether
|
|
|
|
the register is readable and/or writable and is one of:
|
|
|
|
@table @code
|
|
|
|
@item r
|
|
|
|
Read only;
|
|
|
|
|
|
|
|
@item w
|
|
|
|
Write only;
|
|
|
|
|
|
|
|
@item r|w
|
|
|
|
Read and write.
|
|
|
|
|
|
|
|
@end table
|
|
|
|
|
|
|
|
The final parameter, @var{shortcut} indicates whether the register has
|
|
|
|
a short cut in the pipeline. The valid values are:
|
|
|
|
@table @code
|
|
|
|
@item can_shortcut
|
|
|
|
The register has a short cut in the pipeline;
|
|
|
|
|
|
|
|
@item cannot_shortcut
|
|
|
|
The register does not have a short cut in the pipeline.
|
|
|
|
@end table
|
|
|
|
|
|
|
|
For example:
|
|
|
|
@example
|
|
|
|
.extCoreRegister mlo, 57, r , can_shortcut
|
|
|
|
@end example
|
|
|
|
defines a read only extension core register, @code{mlo}, which is
|
|
|
|
register 57, and can short cut the pipeline.
|
|
|
|
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
|
@item .extInstruction @var{name}, @var{opcode}, @var{subopcode}, @var{suffixclass}, @var{syntaxclass}
|
2016-04-06 16:08:04 +02:00
|
|
|
@cindex @code{extInstruction} directive, ARC
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
|
ARC allows the user to specify extension instructions. These
|
|
|
|
extension instructions are not macros; the assembler creates encodings
|
|
|
|
for use of these instructions according to the specification by the
|
|
|
|
user.
|
|
|
|
|
|
|
|
The first argument, @var{name}, gives the name of the instruction.
|
|
|
|
|
|
|
|
The second argument, @var{opcode}, is the opcode to be used (bits 31:27
|
|
|
|
in the encoding).
|
|
|
|
|
|
|
|
The third argument, @var{subopcode}, is the sub-opcode to be used, but
|
|
|
|
the correct value also depends on the fifth argument,
|
|
|
|
@var{syntaxclass}
|
|
|
|
|
|
|
|
The fourth argument, @var{suffixclass}, determines the kinds of
|
|
|
|
suffixes to be allowed. Valid values are:
|
|
|
|
@table @code
|
|
|
|
@item SUFFIX_NONE
|
|
|
|
No suffixes are permitted;
|
|
|
|
|
|
|
|
@item SUFFIX_COND
|
|
|
|
Conditional suffixes are permitted;
|
|
|
|
|
|
|
|
@item SUFFIX_FLAG
|
|
|
|
Flag setting suffixes are permitted.
|
|
|
|
|
|
|
|
@item SUFFIX_COND|SUFFIX_FLAG
|
|
|
|
Both conditional and flag setting suffices are permitted.
|
|
|
|
|
|
|
|
@end table
|
|
|
|
|
|
|
|
The fifth and final argument, @var{syntaxclass}, determines the syntax
|
|
|
|
class for the instruction. It can have the following values:
|
|
|
|
@table @code
|
|
|
|
@item SYNTAX_2OP
|
|
|
|
Two Operand Instruction;
|
|
|
|
|
|
|
|
@item SYNTAX_3OP
|
|
|
|
Three Operand Instruction.
|
2016-05-03 13:44:13 +02:00
|
|
|
|
|
|
|
@item SYNTAX_1OP
|
|
|
|
One Operand Instruction.
|
|
|
|
|
|
|
|
@item SYNTAX_NOP
|
|
|
|
No Operand Instruction.
|
Add support for .extInstruction pseudo-op.
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-04 16:03:53 +02:00
|
|
|
@end table
|
|
|
|
|
|
|
|
The syntax class may be followed by @samp{|} and one of the following
|
|
|
|
modifiers.
|
|
|
|
@table @code
|
|
|
|
|
|
|
|
@item OP1_MUST_BE_IMM
|
|
|
|
Modifies syntax class @code{SYNTAX_3OP}, specifying that the first
|
|
|
|
operand of a three-operand instruction must be an immediate (i.e., the
|
|
|
|
result is discarded). This is usually used to set the flags using
|
|
|
|
specific instructions and not retain results.
|
|
|
|
|
|
|
|
@item OP1_IMM_IMPLIED
|
|
|
|
Modifies syntax class @code{SYNTAX_20P}, specifying that there is an
|
|
|
|
implied immediate destination operand which does not appear in the
|
|
|
|
syntax.
|
|
|
|
|
|
|
|
For example, if the source code contains an instruction like:
|
|
|
|
@example
|
|
|
|
inst r1,r2
|
|
|
|
@end example
|
|
|
|
the first argument is an implied immediate (that is, the result is
|
|
|
|
discarded). This is the same as though the source code were: inst
|
|
|
|
0,r1,r2.
|
|
|
|
|
|
|
|
@end table
|
|
|
|
|
|
|
|
For example, defining a 64-bit multiplier with immediate operands:
|
|
|
|
@example
|
|
|
|
.extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
|
|
|
|
SYNTAX_3OP|OP1_MUST_BE_IMM
|
|
|
|
@end example
|
|
|
|
which specifies an extension instruction named @code{mp64} with 3
|
|
|
|
operands. It sets the flags and can be used with a condition code,
|
|
|
|
for which the first operand is an immediate, i.e. equivalent to
|
|
|
|
discarding the result of the operation.
|
|
|
|
|
|
|
|
A two operands instruction variant would be:
|
|
|
|
@example
|
|
|
|
.extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
|
|
|
|
SYNTAX_2OP|OP1_IMM_IMPLIED
|
|
|
|
@end example
|
|
|
|
which describes a two operand instruction with an implicit first
|
|
|
|
immediate operand. The result of this operation would be discarded.
|
|
|
|
|
[ARC] Object attributes.
gas/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/attr-arc600.d: New file.
* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
* testsuite/gas/arc/attr-arc601.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
* testsuite/gas/arc/attr-arc700.d: Likewise.
* testsuite/gas/arc/attr-arcem.d: Likewise.
* testsuite/gas/arc/attr-archs.d: Likewise.
* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
* testsuite/gas/arc/attr-autodetect-1.s: Likewise.
* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
* testsuite/gas/arc/attr-cpu-a601.s: Likewise.
* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
* testsuite/gas/arc/attr-cpu-a700.s: Likewise.
* testsuite/gas/arc/attr-cpu-em.d: Likewise.
* testsuite/gas/arc/attr-cpu-em.s: Likewise.
* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
* testsuite/gas/arc/attr-cpu-hs.s: Likewise.
* testsuite/gas/arc/attr-em.d: Likewise.
* testsuite/gas/arc/attr-em4.d: Likewise.
* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
* testsuite/gas/arc/attr-hs.d: Likewise.
* testsuite/gas/arc/attr-hs34.d: Likewise.
* testsuite/gas/arc/attr-hs38.d: Likewise.
* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
* testsuite/gas/arc/attr-mul64.d: Likewise.
* testsuite/gas/arc/attr-name.d: Likewise.
* testsuite/gas/arc/attr-name.s: Likewise.
* testsuite/gas/arc/attr-nps400.d: Likewise.
* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
* testsuite/gas/arc/attr-override-mcpu.s
* testsuite/gas/arc/attr-quarkse_em.d: Likewise.
* testsuite/gas/arc/blank.s: Likewise.
* testsuite/gas/elf/section2.e-arc: Likewise.
* testsuite/gas/arc/cpu-pseudop-1.d: Update test.
* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
* testsuite/gas/arc/nps400-0.d: Likewise.
* testsuite/gas/elf/elf.exp: Set target_machine for ARC.
* config/tc-arc.c (opcode/arc-attrs.h): Include.
(ARC_GET_FLAG, ARC_SET_FLAG, streq): Define.
(arc_attribute): Declare new function.
(md_pseudo_table): Add arc_attribute.
(cpu_types): Rename default cpu features.
(selected_cpu): Set the default OSABI flag.
(mpy_option): New variable.
(pic_option): Likewise.
(sda_option): Likewise.
(tls_option): Likewise.
(feature_type, feature_list): Remove.
(arc_initial_eflag): Likewise.
(attributes_set_explicitly): New variable.
(arc_check_feature): Check also for the conflicting features.
(arc_select_cpu): Refactor assignment of selected_cpu.eflags.
(arc_option): Remove setting of private flags and architecture.
(check_cpu_feature): Refactor feature names.
(autodetect_attributes): New function.
(assemble_tokens): Use above function.
(md_parse_option): Refactor feature names.
(arc_attribute): New function.
(arc_set_attribute_int): Likewise.
(arc_set_attribute_string): Likewise.
(arc_stralloc): Likewise.
(arc_set_public_attributes): Likewise.
(arc_md_end): Likewise.
(arc_copy_symbol_attributes): Likewise.
(rc_convert_symbolic_attribute): Likewise.
* config/tc-arc.h (md_end): Define.
(CONVERT_SYMBOLIC_ATTRIBUTE): Likewise.
(TC_COPY_SYMBOL_ATTRIBUTES): Likewise.
* doc/c-arc.texi: Document ARC object attributes.
binutils/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* readelf.c (decode_ARC_machine_flags): Recognize OSABI v4.
(get_arc_section_type_name): New function.
(get_section_type_name): Use the above function.
(display_arc_attribute): New function.
(process_arc_specific): Likewise.
(process_arch_specific): Handle ARC specific information.
* testsuite/binutils-all/strip-3.d: Consider ARC.attributes
section.
include/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* elf/arc.h (SHT_ARC_ATTRIBUTES): Define.
(Tag_ARC_*): Define.
(E_ARC_OSABI_V4): Define.
(E_ARC_OSABI_CURRENT): Reassign it.
(TAG_CPU_*): Define.
* opcode/arc-attrs.h: New file.
* opcode/arc.h (insn_subclass_t): Assign enum values.
(insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64.
(ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT)
(ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP)
(ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW)
(ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC)
(ARC_CRC): Delete.
bfd/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* elf32-arc.c (FEATURE_LIST_NAME): Define.
(CONFLICT_LIST): Likewise.
(opcode/arc-attrs.h): Include.
(arc_elf_print_private_bfd_data): Print OSABI v4 flag.
(arc_extract_features): New file.
(arc_stralloc): Likewise.
(arc_elf_merge_attributes): Likewise.
(arc_elf_merge_private_bfd_data): Use object attributes.
(bfd_arc_get_mach_from_attributes): New function.
(arc_elf_object_p): Use object attributes.
(arc_elf_final_write_processing): Likewise.
(elf32_arc_obj_attrs_arg_type): New function.
(elf32_arc_obj_attrs_handle_unknown): Likewise.
(elf32_arc_section_from_shdr): Likewise.
(elf_backend_obj_attrs_vendor): Define.
(elf_backend_obj_attrs_section): Likewise.
(elf_backend_obj_attrs_arg_type): Likewise.
(elf_backend_obj_attrs_section_type): Likewise.
(elf_backend_obj_attrs_handle_unknown): Likewise.
(elf_backend_section_from_shdr): Likewise.
ld/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/ld-arc/attr-merge-0.d: New file.
* testsuite/ld-arc/attr-merge-0.s: Likewise.
* testsuite/ld-arc/attr-merge-0e.s: Likewise.
* testsuite/ld-arc/attr-merge-1.d: Likewise.
* testsuite/ld-arc/attr-merge-1.s: Likewise.
* testsuite/ld-arc/attr-merge-1e.s: Likewise.
* testsuite/ld-arc/attr-merge-2.d: Likewise.
* testsuite/ld-arc/attr-merge-2.s: Likewise.
* testsuite/ld-arc/attr-merge-3.d: Likewise.
* testsuite/ld-arc/attr-merge-3.s: Likewise.
* testsuite/ld-arc/attr-merge-3e.s: Likewise.
* testsuite/ld-arc/attr-merge-4.s: Likewise.
* testsuite/ld-arc/attr-merge-5.d: Likewise.
* testsuite/ld-arc/attr-merge-5a.s: Likewise.
* testsuite/ld-arc/attr-merge-5b.s: Likewise.
* testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise.
* testsuite/ld-arc/attr-merge-err-isa.d: Likewise.
* testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise.
* testsuite/ld-arc/got-01.d: Update test.
* testsuite/ld-arc/attr-merge-err-quarkse.d: New file.
* testsuite/ld-arc/attr-quarkse.s: Likewise.
* testsuite/ld-arc/attr-quarkse2.s: Likewise.
opcodes/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (parse_option): Update quarkse_em option..
* arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
QUARKSE1.
(dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
2017-05-10 14:42:22 +02:00
|
|
|
@cindex @code{.arc_attribute} directive, ARC
|
|
|
|
@item .arc_attribute @var{tag}, @var{value}
|
|
|
|
Set the ARC object attribute @var{tag} to @var{value}.
|
|
|
|
|
|
|
|
The @var{tag} is either an attribute number, or one of the following:
|
|
|
|
@code{Tag_ARC_PCS_config}, @code{Tag_ARC_CPU_base},
|
|
|
|
@code{Tag_ARC_CPU_variation}, @code{Tag_ARC_CPU_name},
|
|
|
|
@code{Tag_ARC_ABI_rf16}, @code{Tag_ARC_ABI_osver}, @code{Tag_ARC_ABI_sda},
|
|
|
|
@code{Tag_ARC_ABI_pic}, @code{Tag_ARC_ABI_tls}, @code{Tag_ARC_ABI_enumsize},
|
|
|
|
@code{Tag_ARC_ABI_exceptions}, @code{Tag_ARC_ABI_double_size},
|
|
|
|
@code{Tag_ARC_ISA_config}, @code{Tag_ARC_ISA_apex},
|
|
|
|
@code{Tag_ARC_ISA_mpy_option}
|
|
|
|
|
|
|
|
The @var{value} is either a @code{number}, @code{"string"}, or
|
|
|
|
@code{number, "string"} depending on the tag.
|
|
|
|
|
2005-02-28 19:05:06 +01:00
|
|
|
@end table
|
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
@node ARC Modifiers
|
|
|
|
@section ARC Assembler Modifiers
|
2005-02-28 19:05:06 +01:00
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
The following additional assembler modifiers have been added for
|
|
|
|
position-independent code. These modifiers are available only with
|
|
|
|
the ARC 700 and above processors and generate relocation entries,
|
|
|
|
which are interpreted by the linker as follows:
|
2005-02-28 19:05:06 +01:00
|
|
|
|
|
|
|
@table @code
|
2015-10-07 15:20:19 +02:00
|
|
|
@item @@pcl(@var{symbol})
|
|
|
|
@cindex @@pcl(@var{symbol}), ARC modifier
|
|
|
|
Relative distance of @var{symbol}'s from the current program counter
|
|
|
|
location.
|
|
|
|
|
|
|
|
@item @@gotpc(@var{symbol})
|
|
|
|
@cindex @@gotpc(@var{symbol}), ARC modifier
|
|
|
|
Relative distance of @var{symbol}'s Global Offset Table entry from the
|
|
|
|
current program counter location.
|
|
|
|
|
|
|
|
@item @@gotoff(@var{symbol})
|
|
|
|
@cindex @@gotoff(@var{symbol}), ARC modifier
|
|
|
|
Distance of @var{symbol} from the base of the Global Offset Table.
|
|
|
|
|
|
|
|
@item @@plt(@var{symbol})
|
|
|
|
@cindex @@plt(@var{symbol}), ARC modifier
|
|
|
|
Distance of @var{symbol}'s Procedure Linkage Table entry from the
|
|
|
|
current program counter. This is valid only with branch and link
|
|
|
|
instructions and PC-relative calls.
|
|
|
|
|
|
|
|
@item @@sda(@var{symbol})
|
|
|
|
@cindex @@sda(@var{symbol}), ARC modifier
|
|
|
|
Relative distance of @var{symbol} from the base of the Small Data
|
|
|
|
Pointer.
|
2005-02-28 19:05:06 +01:00
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
@end table
|
2001-01-12 18:50:59 +01:00
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
@node ARC Symbols
|
|
|
|
@section ARC Pre-defined Symbols
|
2001-01-12 18:50:59 +01:00
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
The following assembler symbols will prove useful when developing
|
|
|
|
position-independent code. These symbols are available only with the
|
|
|
|
ARC 700 and above processors.
|
2001-01-12 18:50:59 +01:00
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
@table @code
|
|
|
|
@item __GLOBAL_OFFSET_TABLE__
|
|
|
|
@cindex __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol
|
|
|
|
Symbol referring to the base of the Global Offset Table.
|
2001-01-12 18:50:59 +01:00
|
|
|
|
2015-10-07 15:20:19 +02:00
|
|
|
@item __DYNAMIC__
|
|
|
|
@cindex __DYNAMIC__, ARC pre-defined symbol
|
|
|
|
An alias for the Global Offset Table
|
|
|
|
@code{Base__GLOBAL_OFFSET_TABLE__}. It can be used only with
|
|
|
|
@code{@@gotpc} modifiers.
|
2001-01-12 18:50:59 +01:00
|
|
|
|
|
|
|
@end table
|
|
|
|
|
|
|
|
@node ARC Opcodes
|
|
|
|
@section Opcodes
|
|
|
|
|
|
|
|
@cindex ARC opcodes
|
|
|
|
@cindex opcodes for ARC
|
|
|
|
|
|
|
|
For information on the ARC instruction set, see @cite{ARC Programmers
|
2015-10-07 15:20:19 +02:00
|
|
|
Reference Manual}, available where you download the processor IP library.
|