2001-05-20 17:40:27 +02:00
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/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
|
* sim-main.h (cpu_frame, cpu_frame_list): Remove.
(cpu_frame_reg, cpu_print_frame): Remove.
(cpu_m68hc11_push_uint8, cpu_m68hc11_pop_uint8): Cleanup.
(cpu_m68hc11_push_uint16, cpu_m68hc11_pop_uint16): Likewise.
(cpu_m68hc12_push_uint8, cpu_m68hc12_push_uint16): Likewise.
(cpu_m68hc12_pop_uint8, cpu_m68hc12_pop_uint16): Likewise.
* m68hc11_sim.c (cpu_find_frame): Remove.
(cpu_create_frame_list): Remove.
(cpu_remove_frame_list, cpu_create_frame, cpu_free_frame): Remove.
(cpu_frame_reg, cpu_print_frame, cpu_update_frame): Remove.
(cpu_call): Cleanup to remove #if HAVE_FRAME and calls to the above.
(cpu_update_frame): Likewise.
(cpu_return): Likewise.
(cpu_reset): Likewise.
(cpu_initialize): Likewise.
* interp.c (sim_do_command): Remove call to cpu_print_frame.
2002-03-07 20:06:34 +01:00
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Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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2000-07-27 13:23:39 +02:00
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Written by Stephane Carrez (stcarrez@worldnet.fr)
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef _SIM_MAIN_H
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#define _SIM_MAIN_H
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#define WITH_MODULO_MEMORY 1
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#define WITH_WATCHPOINTS 1
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#define SIM_HANDLES_LMA 1
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#include "sim-basics.h"
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typedef address_word sim_cia;
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#include "sim-signal.h"
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#include "sim-base.h"
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#include "bfd.h"
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#include "opcode/m68hc11.h"
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2002-06-09 17:45:54 +02:00
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#include "gdb/callback.h"
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#include "gdb/remote-sim.h"
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2000-07-27 13:23:39 +02:00
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#include "opcode/m68hc11.h"
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#include "sim-types.h"
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typedef unsigned8 uint8;
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typedef unsigned16 uint16;
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typedef signed16 int16;
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typedef unsigned32 uint32;
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typedef signed32 int32;
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typedef unsigned64 uint64;
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typedef signed64 int64;
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struct _sim_cpu;
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#include "interrupts.h"
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#include <setjmp.h>
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2000-08-11 20:44:59 +02:00
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/* Specifies the level of mapping for the IO, EEprom, nvram and external
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RAM. IO registers are mapped over everything and the external RAM
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is last (ie, it can be hidden by everything above it in the list). */
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enum m68hc11_map_level
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{
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M6811_IO_LEVEL,
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M6811_EEPROM_LEVEL,
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M6811_NVRAM_LEVEL,
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M6811_RAM_LEVEL
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};
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2001-05-20 17:40:27 +02:00
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enum cpu_type
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{
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CPU_M6811,
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CPU_M6812
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};
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2000-08-11 20:44:59 +02:00
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2000-07-27 13:23:39 +02:00
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#define X_REGNUM 0
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#define D_REGNUM 1
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#define Y_REGNUM 2
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#define SP_REGNUM 3
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#define PC_REGNUM 4
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#define A_REGNUM 5
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#define B_REGNUM 6
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#define PSW_REGNUM 7
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#define Z_REGNUM 8
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typedef struct m6811_regs {
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unsigned short d;
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unsigned short ix;
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unsigned short iy;
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unsigned short sp;
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unsigned short pc;
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unsigned char ccr;
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} m6811_regs;
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/* Description of 68HC11 IO registers. Such description is only provided
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for the info command to display the current setting of IO registers
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from GDB. */
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struct io_reg_desc
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{
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int mask;
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const char *short_name;
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const char *long_name;
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};
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typedef struct io_reg_desc io_reg_desc;
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extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
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int mode);
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extern void print_io_byte (SIM_DESC sd, const char *name,
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io_reg_desc *desc, uint8 val, uint16 addr);
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2001-05-20 17:40:27 +02:00
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/* List of special 68HC11&68HC12 instructions that are not handled by the
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2000-07-27 13:23:39 +02:00
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'gencode.c' generator. These complex instructions are implemented
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by 'cpu_special'. */
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enum M6811_Special
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{
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2001-05-20 17:40:27 +02:00
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/* 68HC11 instructions. */
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M6811_DAA,
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M6811_EMUL_SYSCALL,
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M6811_ILLEGAL,
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2000-07-27 13:23:39 +02:00
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M6811_RTI,
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2001-05-20 17:40:27 +02:00
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M6811_STOP,
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2000-07-27 13:23:39 +02:00
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M6811_SWI,
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M6811_TEST,
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2001-05-20 17:40:27 +02:00
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M6811_WAI,
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/* 68HC12 instructions. */
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M6812_BGND,
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M6812_CALL,
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M6812_IDIVS,
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M6812_EDIV,
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M6812_EDIVS,
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M6812_EMACS,
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M6812_EMUL,
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M6812_EMULS,
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M6812_ETBL,
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M6812_MEM,
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M6812_REV,
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M6812_REVW,
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M6812_RTC,
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M6812_RTI,
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M6812_WAV
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2000-07-27 13:23:39 +02:00
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};
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2001-05-20 17:40:27 +02:00
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#define M6811_MAX_PORTS (0x03f+1)
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#define M6812_MAX_PORTS (0x3ff+1)
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#define MAX_PORTS (M6812_MAX_PORTS)
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2000-07-27 13:23:39 +02:00
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2001-05-20 17:40:27 +02:00
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struct _sim_cpu;
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typedef void (* cpu_interp) (struct _sim_cpu*);
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2000-07-27 13:23:39 +02:00
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struct _sim_cpu {
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/* CPU registers. */
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struct m6811_regs cpu_regs;
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/* CPU interrupts. */
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struct interrupts cpu_interrupts;
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2001-05-20 17:40:27 +02:00
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/* Pointer to the interpretor routine. */
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cpu_interp cpu_interpretor;
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/* Pointer to the architecture currently configured in the simulator. */
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const struct bfd_arch_info *cpu_configured_arch;
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2000-07-27 13:23:39 +02:00
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/* CPU absolute cycle time. The cycle time is updated after
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each instruction, by the number of cycles taken by the instruction.
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It is cleared only when reset occurs. */
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signed64 cpu_absolute_cycle;
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/* Number of cycles to increment after the current instruction.
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This is also the number of ticks for the generic event scheduler. */
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uint8 cpu_current_cycle;
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int cpu_emul_syscall;
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int cpu_is_initialized;
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int cpu_running;
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int cpu_check_memory;
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int cpu_stop_on_interrupt;
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/* When this is set, start execution of program at address specified
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in the ELF header. This is used for testing some programs that do not
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have an interrupt table linked with them. Programs created during the
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GCC validation are like this. A normal 68HC11 does not behave like
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this (unless there is some OS or downloadable feature). */
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int cpu_use_elf_start;
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/* The starting address specified in ELF header. */
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int cpu_elf_start;
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uint16 cpu_insn_pc;
|
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/* CPU frequency. This is the quartz frequency. It is divided by 4 to
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|
get the cycle time. This is used for the timer rate and for the baud
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|
rate generation. */
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unsigned long cpu_frequency;
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/* The mode in which the CPU is configured (MODA and MODB pins). */
|
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|
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unsigned int cpu_mode;
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|
2001-05-20 17:40:27 +02:00
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/* The cpu being configured. */
|
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enum cpu_type cpu_type;
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2000-07-27 13:23:39 +02:00
|
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|
/* Initial value of the CONFIG register. */
|
|
|
|
uint8 cpu_config;
|
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uint8 cpu_use_local_config;
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|
2001-05-20 17:40:27 +02:00
|
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uint8 ios[MAX_PORTS];
|
2002-03-07 20:12:44 +01:00
|
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struct hw *hw_cpu;
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2000-07-27 13:23:39 +02:00
|
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/* ... base type ... */
|
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sim_cpu_base base;
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};
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/* Returns the cpu absolute cycle time (A virtual counter incremented
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at each 68HC11 E clock). */
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#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
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#define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
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#define cpu_is_running(PROC) ((PROC)->cpu_running)
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/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
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#define cpu_get_io_base(PROC) \
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(((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
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|
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#define cpu_get_reg_base(PROC) \
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(((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
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/* Returns the different CPU registers. */
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#define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
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#define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
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#define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
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#define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
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#define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
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#define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
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#define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
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#define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
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|
2001-05-20 17:40:27 +02:00
|
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/* 68HC12 specific and Motorola internal registers. */
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#define cpu_get_tmp3(PROC) (0)
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#define cpu_get_tmp2(PROC) (0)
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|
2000-07-27 13:23:39 +02:00
|
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#define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
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#define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
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#define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
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2001-05-20 17:40:27 +02:00
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/* 68HC12 specific and Motorola internal registers. */
|
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#define cpu_set_tmp3(PROC,VAL) (0)
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#define cpu_set_tmp2(PROC,VAL) (0)
|
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2000-07-27 13:23:39 +02:00
|
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#if 0
|
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|
|
/* This is a function in m68hc11_sim.c to keep track of the frame. */
|
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#define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
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#endif
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#define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
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#define cpu_set_a(PROC,VAL) \
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cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
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#define cpu_set_b(PROC,VAL) \
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cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))
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#define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
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#define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
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#define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
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#define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
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#define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
|
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#define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
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#define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
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|
#define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
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#define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
|
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|
#define cpu_set_ccr_flag(S,B,V) \
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cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))
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|
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#define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
|
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|
|
#define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
|
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|
|
#define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
|
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|
#define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
|
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|
|
#define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
|
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|
|
#define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
|
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|
|
#define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
|
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|
|
#define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
|
|
|
|
|
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|
|
#undef inline
|
|
|
|
#define inline static __inline__
|
|
|
|
|
|
|
|
extern void cpu_memory_exception (struct _sim_cpu *proc,
|
|
|
|
SIM_SIGNAL excep,
|
|
|
|
uint16 addr,
|
|
|
|
const char *message);
|
|
|
|
|
|
|
|
inline uint8
|
|
|
|
memory_read8 (sim_cpu *cpu, uint16 addr)
|
|
|
|
{
|
|
|
|
uint8 val;
|
|
|
|
|
|
|
|
if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
|
|
|
|
{
|
|
|
|
cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
|
|
|
|
"Read error");
|
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline void
|
|
|
|
memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
|
|
|
|
{
|
|
|
|
if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
|
|
|
|
{
|
|
|
|
cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
|
|
|
|
"Write error");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
inline uint16
|
|
|
|
memory_read16 (sim_cpu *cpu, uint16 addr)
|
|
|
|
{
|
|
|
|
uint8 b[2];
|
|
|
|
|
|
|
|
if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
|
|
|
|
{
|
|
|
|
cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
|
|
|
|
"Read error");
|
|
|
|
}
|
|
|
|
return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
|
|
|
|
}
|
|
|
|
|
|
|
|
inline void
|
|
|
|
memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
|
|
|
|
{
|
|
|
|
uint8 b[2];
|
|
|
|
|
|
|
|
b[0] = val >> 8;
|
|
|
|
b[1] = val;
|
|
|
|
if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
|
|
|
|
{
|
|
|
|
cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
|
|
|
|
"Write error");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
extern void
|
|
|
|
cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
|
|
|
|
|
|
|
|
inline void
|
|
|
|
cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
|
|
|
|
{
|
|
|
|
cpu_set_ccr_V (proc, 0);
|
|
|
|
cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
|
|
|
|
cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
inline void
|
|
|
|
cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
|
|
|
|
{
|
|
|
|
cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
|
|
|
|
cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
|
|
|
|
cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
|
|
|
|
}
|
|
|
|
|
|
|
|
inline void
|
|
|
|
cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
|
|
|
|
{
|
|
|
|
cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
|
|
|
|
cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
|
|
|
|
cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
|
|
|
|
}
|
|
|
|
|
|
|
|
inline void
|
|
|
|
cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
|
|
|
|
{
|
|
|
|
cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
|
|
|
|
cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
|
|
|
|
cpu_set_ccr_Z (proc, r == 0);
|
|
|
|
cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
inline void
|
|
|
|
cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
|
|
|
|
{
|
|
|
|
cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
|
|
|
|
cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
|
|
|
|
cpu_set_ccr_Z (proc, r == 0);
|
|
|
|
cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
inline void
|
|
|
|
cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
|
|
|
|
{
|
|
|
|
cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
|
|
|
|
cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
|
|
|
|
cpu_set_ccr_Z (proc, r == 0);
|
|
|
|
cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
inline void
|
|
|
|
cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
|
|
|
|
{
|
|
|
|
cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
|
|
|
|
cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
|
|
|
|
cpu_set_ccr_Z (proc, r == 0);
|
|
|
|
cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
|
|
|
|
}
|
|
|
|
|
2001-05-20 17:40:27 +02:00
|
|
|
/* Push and pop instructions for 68HC11 (next-available stack mode). */
|
2000-07-27 13:23:39 +02:00
|
|
|
inline void
|
2001-05-20 17:40:27 +02:00
|
|
|
cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
|
2000-07-27 13:23:39 +02:00
|
|
|
{
|
|
|
|
uint16 addr = proc->cpu_regs.sp;
|
|
|
|
|
|
|
|
memory_write8 (proc, addr, val);
|
|
|
|
proc->cpu_regs.sp = addr - 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline void
|
2001-05-20 17:40:27 +02:00
|
|
|
cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
|
2000-07-27 13:23:39 +02:00
|
|
|
{
|
|
|
|
uint16 addr = proc->cpu_regs.sp - 1;
|
|
|
|
|
|
|
|
memory_write16 (proc, addr, val);
|
|
|
|
proc->cpu_regs.sp = addr - 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline uint8
|
2001-05-20 17:40:27 +02:00
|
|
|
cpu_m68hc11_pop_uint8 (sim_cpu *proc)
|
2000-07-27 13:23:39 +02:00
|
|
|
{
|
|
|
|
uint16 addr = proc->cpu_regs.sp;
|
|
|
|
uint8 val;
|
|
|
|
|
|
|
|
val = memory_read8 (proc, addr + 1);
|
|
|
|
proc->cpu_regs.sp = addr + 1;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline uint16
|
2001-05-20 17:40:27 +02:00
|
|
|
cpu_m68hc11_pop_uint16 (sim_cpu *proc)
|
2000-07-27 13:23:39 +02:00
|
|
|
{
|
|
|
|
uint16 addr = proc->cpu_regs.sp;
|
|
|
|
uint16 val;
|
|
|
|
|
|
|
|
val = memory_read16 (proc, addr + 1);
|
|
|
|
proc->cpu_regs.sp = addr + 2;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2001-05-20 17:40:27 +02:00
|
|
|
/* Push and pop instructions for 68HC12 (last-used stack mode). */
|
|
|
|
inline void
|
|
|
|
cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
|
|
|
|
{
|
|
|
|
uint16 addr = proc->cpu_regs.sp;
|
|
|
|
|
|
|
|
addr --;
|
|
|
|
memory_write8 (proc, addr, val);
|
|
|
|
proc->cpu_regs.sp = addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline void
|
|
|
|
cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
|
|
|
|
{
|
|
|
|
uint16 addr = proc->cpu_regs.sp;
|
|
|
|
|
|
|
|
addr -= 2;
|
|
|
|
memory_write16 (proc, addr, val);
|
|
|
|
proc->cpu_regs.sp = addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline uint8
|
|
|
|
cpu_m68hc12_pop_uint8 (sim_cpu *proc)
|
|
|
|
{
|
|
|
|
uint16 addr = proc->cpu_regs.sp;
|
|
|
|
uint8 val;
|
|
|
|
|
|
|
|
val = memory_read8 (proc, addr);
|
|
|
|
proc->cpu_regs.sp = addr + 1;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline uint16
|
|
|
|
cpu_m68hc12_pop_uint16 (sim_cpu *proc)
|
|
|
|
{
|
|
|
|
uint16 addr = proc->cpu_regs.sp;
|
|
|
|
uint16 val;
|
|
|
|
|
|
|
|
val = memory_read16 (proc, addr);
|
|
|
|
proc->cpu_regs.sp = addr + 2;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fetch a 8/16 bit value and update the PC. */
|
2000-07-27 13:23:39 +02:00
|
|
|
inline uint8
|
|
|
|
cpu_fetch8 (sim_cpu *proc)
|
|
|
|
{
|
|
|
|
uint16 addr = proc->cpu_regs.pc;
|
|
|
|
uint8 val;
|
|
|
|
|
|
|
|
val = memory_read8 (proc, addr);
|
|
|
|
proc->cpu_regs.pc = addr + 1;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline uint16
|
|
|
|
cpu_fetch16 (sim_cpu *proc)
|
|
|
|
{
|
|
|
|
uint16 addr = proc->cpu_regs.pc;
|
|
|
|
uint16 val;
|
|
|
|
|
|
|
|
val = memory_read16 (proc, addr);
|
|
|
|
proc->cpu_regs.pc = addr + 2;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
extern void cpu_call (sim_cpu* proc, uint16 addr);
|
2001-05-20 17:40:27 +02:00
|
|
|
extern void cpu_exg (sim_cpu* proc, uint8 code);
|
|
|
|
extern void cpu_dbcc (sim_cpu* proc);
|
2000-07-27 13:23:39 +02:00
|
|
|
extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
|
2001-05-20 17:40:27 +02:00
|
|
|
extern void cpu_move8 (sim_cpu *proc, uint8 op);
|
|
|
|
extern void cpu_move16 (sim_cpu *proc, uint8 op);
|
2000-07-27 13:23:39 +02:00
|
|
|
|
|
|
|
extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
|
2001-05-20 17:40:27 +02:00
|
|
|
extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
|
2000-07-27 13:23:39 +02:00
|
|
|
extern void cpu_push_all (sim_cpu *proc);
|
|
|
|
extern void cpu_single_step (sim_cpu *proc);
|
|
|
|
|
|
|
|
extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
|
|
|
|
|
|
|
|
extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
|
|
|
|
|
|
|
|
extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
|
|
|
|
extern int cpu_reset (sim_cpu *cpu);
|
|
|
|
extern int cpu_restart (sim_cpu *cpu);
|
|
|
|
extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
|
|
|
|
uint16 addr, const char *message, ...);
|
|
|
|
extern void emul_os (int op, sim_cpu *cpu);
|
2001-05-20 17:40:27 +02:00
|
|
|
extern void cpu_interp_m6811 (sim_cpu *cpu);
|
|
|
|
extern void cpu_interp_m6812 (sim_cpu *cpu);
|
2000-07-27 13:23:39 +02:00
|
|
|
|
2002-03-07 20:12:44 +01:00
|
|
|
extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
|
|
|
|
double ton, double toff,
|
|
|
|
signed64 repeat);
|
|
|
|
extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
|
|
|
|
extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
|
|
|
|
unsigned addr, uint8 val);
|
|
|
|
|
2000-07-27 13:23:39 +02:00
|
|
|
/* The current state of the processor; registers, memory, etc. */
|
|
|
|
|
|
|
|
#define CIA_GET(CPU) (cpu_get_pc (CPU))
|
|
|
|
#define CIA_SET(CPU,VAL) (cpu_set_pc ((CPU), (VAL)))
|
|
|
|
|
|
|
|
#if (WITH_SMP)
|
|
|
|
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
|
|
|
|
#else
|
|
|
|
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
|
|
|
|
#endif
|
|
|
|
|
|
|
|
struct sim_state {
|
|
|
|
sim_cpu cpu[MAX_NR_PROCESSORS];
|
|
|
|
device *devices;
|
|
|
|
sim_state_base base;
|
|
|
|
};
|
|
|
|
|
|
|
|
extern void sim_set_profile (int n);
|
|
|
|
extern void sim_set_profile_size (int n);
|
|
|
|
extern void sim_board_reset (SIM_DESC sd);
|
|
|
|
|
2000-09-09 23:00:39 +02:00
|
|
|
extern const char *cycle_to_string (sim_cpu *cpu, signed64 t);
|
|
|
|
|
2000-07-27 13:23:39 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|