2017-07-11 11:43:08 +02:00
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/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
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2014-04-22 16:57:47 +02:00
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/* Semantic operand instances for or1k.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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2020-01-01 08:57:01 +01:00
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Copyright (C) 1996-2020 Free Software Foundation, Inc.
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2014-04-22 16:57:47 +02:00
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "sysdep.h"
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#include "ansidecl.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "or1k-desc.h"
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#include "or1k-opc.h"
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/* Operand references. */
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#define OP_ENT(op) OR1K_OPERAND_##op
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#define INPUT CGEN_OPINST_INPUT
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#define OUTPUT CGEN_OPINST_OUTPUT
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#define END CGEN_OPINST_END
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#define COND_REF CGEN_OPINST_COND_REF
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static const CGEN_OPINST sfmt_empty_ops[] ATTRIBUTE_UNUSED = {
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_j_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, 0 },
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{ INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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or1k: Add the l.adrp insn and supporting relocations
This patch adds the new instruction and relocation as per proposal:
https://openrisc.io/proposals/ladrp
This is to be added to the spec in an upcoming revision. The new instruction
l.adrp loads the page offset of the current instruction offset by
a 21-bit immediate shifted left 13-bits. This is meant to be used with
a 13-bit lower bit page offset. This allows us to free up the got
register r16.
l.adrp r3, foo
l.ori r4, r3, po(foo)
l.lbz r5, po(foo)(r3)
l.sb po(foo)(r3), r6
The relocations we add are:
- BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry
asm: plta() implemented using l.ardp, meaning
no need for r16 (the GOT reg)
- BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address
asm: got()
- BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General
asm: tlsgd() Dynamic calculation
- BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local
asm: tlsldm() dynamic calculation
- BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial
asm: gottp() Executable calculation
- BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp
instructions)
- BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation
asm: po() i.e. mem loads, addi etc
- BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation
asm: po() i.e. mem stores, with split immediate
- BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs
asm: gotpo()
- BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs
asm: tlsgdpo()
- BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs
asm: tlsldmpo()
- BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs
asm: gottppo()
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* bfd-in2.h: Regenerated.
* elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for
R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21,
R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21,
R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13,
R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26.
(or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21,
BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26.
(elf_or1k_link_hash_table): Add field saw_plta.
(or1k_final_link_relocate): Add value calculations for new relocations.
(or1k_elf_relocate_section): Add section relocations for new
relocations.
(or1k_write_plt_entry): New function.
(or1k_elf_finish_dynamic_sections): Add support for PLTA relocations
using new l.adrp instruction. Cleanup PLT relocation code generation.
* libbfd.h: Regenerated.
* reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc (parse_disp26): Add support for plta() relocations.
(parse_disp21): New function.
(or1k_rclass): New enum.
(or1k_rtype): New enum.
(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
(parse_imm16): Add support for the new 21bit and 13bit relocations.
* or1korbis.cpu (f-disp26): Don't assume SI.
(f-disp21): New pc-relative 21-bit 13 shifted to right.
(insn-opcode): Add ADRP.
(l-adrp): New instruction.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
* testsuite/gas/or1k/allinsn.s: Add test for l.adrp.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
* testsuite/gas/or1k/reloc-1.s: Add tests to generate
R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13,
R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13
relocations.
* testsuite/gas/or1k/reloc-1.d: Add relocation results for
tests.
* testsuite/gas/or1k/reloc-2.s: Add negative tests for store to
gotpo().
* testsuite/gas/or1k/reloc-2.l: Add expected error test results.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/or1k.exp: Add test cases for plt generation.
* testsuite/ld-or1k/plt1.dd: New file.
* testsuite/ld-or1k/plt1.s: New file.
* testsuite/ld-or1k/plt1.x.dd: New file.
* testsuite/ld-or1k/plta1.dd: New file.
* testsuite/ld-or1k/plta1.s: New file.
* testsuite/ld-or1k/pltlib.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
R_OR1K_SLO13, R_OR1K_PLTA26.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerated.
* or1k-desc.c: Regenerated.
* or1k-desc.h: Regenerated.
* or1k-dis.c: Regenerated.
* or1k-ibld.c: Regenerated.
* or1k-opc.c: Regenerated.
* or1k-opc.h: Regenerated.
* or1k-opinst.c: Regenerated.
2018-10-05 04:41:41 +02:00
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static const CGEN_OPINST sfmt_l_adrp_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "disp21", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP21), 0, 0 },
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{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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2014-04-22 16:57:47 +02:00
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static const CGEN_OPINST sfmt_l_jal_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, 0 },
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{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
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{ INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 },
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{ OUTPUT, "h_gpr_UDI_9", HW_H_GPR, CGEN_MODE_UDI, 0, 9, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_jr_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
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{ INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_jalr_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
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{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
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{ INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 },
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{ OUTPUT, "h_gpr_UDI_9", HW_H_GPR, CGEN_MODE_UDI, 0, 9, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_bnf_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, COND_REF },
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{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
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{ INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, COND_REF },
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{ INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
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{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_trap_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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2014-07-20 19:26:09 +02:00
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static const CGEN_OPINST sfmt_l_msync_ops[] ATTRIBUTE_UNUSED = {
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2014-04-22 16:57:47 +02:00
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_nop_imm_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_movhi_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
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{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_macrc_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
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{ OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
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{ OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
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{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_mfspr_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
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{ INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
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{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_mtspr_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
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{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
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{ INPUT, "uimm16_split", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16_SPLIT), 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_lwz_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
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{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
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{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
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{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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static const CGEN_OPINST sfmt_l_lws_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "h_memory_SI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
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{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
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{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
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{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
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{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
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};
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2014-05-08 07:53:09 +02:00
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static const CGEN_OPINST sfmt_l_lwa_ops[] ATTRIBUTE_UNUSED = {
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{ INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
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{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
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{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
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{ OUTPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2014-04-22 16:57:47 +02:00
|
|
|
static const CGEN_OPINST sfmt_l_lbz_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "h_memory_UQI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_lbs_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "h_memory_QI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_lhz_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "h_memory_UHI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_2", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_lhs_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "h_memory_HI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_sw_ops[] ATTRIBUTE_UNUSED = {
|
2014-05-08 07:53:09 +02:00
|
|
|
{ INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
|
2014-05-08 07:53:09 +02:00
|
|
|
{ OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
|
|
|
|
{ OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_sb_ops[] ATTRIBUTE_UNUSED = {
|
2014-05-08 07:53:09 +02:00
|
|
|
{ INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
|
2014-05-08 07:53:09 +02:00
|
|
|
{ OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
|
|
|
|
{ OUTPUT, "h_memory_UQI_addr", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_sh_ops[] ATTRIBUTE_UNUSED = {
|
2014-05-08 07:53:09 +02:00
|
|
|
{ INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
|
2014-05-08 07:53:09 +02:00
|
|
|
{ OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF },
|
|
|
|
{ OUTPUT, "h_memory_UHI_addr", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_swa_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 },
|
|
|
|
{ INPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF },
|
|
|
|
{ INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, COND_REF },
|
|
|
|
{ OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_sll_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_slli_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "uimm6", HW_H_UIMM6, CGEN_MODE_UINT, OP_ENT (UIMM6), 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_and_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_add_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_addc_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
static const CGEN_OPINST sfmt_l_mul_ops[] ATTRIBUTE_UNUSED = {
|
2014-04-22 16:57:47 +02:00
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_muld_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_mulu_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_div_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF },
|
|
|
|
{ OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_divu_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, COND_REF },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF },
|
|
|
|
{ OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_ff1_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_xori_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_addi_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_addic_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
static const CGEN_OPINST sfmt_l_muli_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2014-04-22 16:57:47 +02:00
|
|
|
static const CGEN_OPINST sfmt_l_exths_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_cmov_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF },
|
|
|
|
{ INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_sfgts_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_sfgtsi_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_mac_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
{ INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
{ OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_maci_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
{ INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
{ OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_l_macu_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF },
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 },
|
2014-04-22 16:57:47 +02:00
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_lf_add_s_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
|
|
|
|
{ INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 },
|
|
|
|
{ OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_lf_add_d_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 },
|
|
|
|
{ INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 },
|
|
|
|
{ OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2019-06-12 23:16:19 +02:00
|
|
|
static const CGEN_OPINST sfmt_lf_add_d32_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
|
|
|
|
{ INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
|
|
|
|
{ OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2014-04-22 16:57:47 +02:00
|
|
|
static const CGEN_OPINST sfmt_lf_itof_s_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_lf_itof_d_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
|
|
|
|
{ INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2019-06-12 23:16:19 +02:00
|
|
|
static const CGEN_OPINST sfmt_lf_itof_d32_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rADI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RADI), 0, 0 },
|
|
|
|
{ INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2014-04-22 16:57:47 +02:00
|
|
|
static const CGEN_OPINST sfmt_lf_ftoi_s_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
|
|
|
|
{ INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_lf_ftoi_d_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 },
|
|
|
|
{ INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2019-06-12 23:16:19 +02:00
|
|
|
static const CGEN_OPINST sfmt_lf_ftoi_d32_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
|
|
|
|
{ INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ OUTPUT, "rDDI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RDDI), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_lf_sfeq_s_ops[] ATTRIBUTE_UNUSED = {
|
2014-04-22 16:57:47 +02:00
|
|
|
{ INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
|
|
|
|
{ INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2019-06-12 23:16:19 +02:00
|
|
|
static const CGEN_OPINST sfmt_lf_sfeq_d_ops[] ATTRIBUTE_UNUSED = {
|
2014-04-22 16:57:47 +02:00
|
|
|
{ INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 },
|
|
|
|
{ INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2019-06-12 23:16:19 +02:00
|
|
|
static const CGEN_OPINST sfmt_lf_sfeq_d32_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
|
|
|
|
{ INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
|
|
|
|
{ OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2014-04-22 16:57:47 +02:00
|
|
|
static const CGEN_OPINST sfmt_lf_madd_s_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
|
|
|
|
{ INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 },
|
|
|
|
{ INPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 },
|
|
|
|
{ OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const CGEN_OPINST sfmt_lf_madd_d_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 },
|
|
|
|
{ INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 },
|
|
|
|
{ INPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 },
|
|
|
|
{ OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2019-06-12 23:16:19 +02:00
|
|
|
static const CGEN_OPINST sfmt_lf_madd_d32_ops[] ATTRIBUTE_UNUSED = {
|
|
|
|
{ INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
|
|
|
|
{ INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
|
|
|
|
{ INPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
|
|
|
|
{ OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
|
|
|
|
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
|
|
|
|
};
|
|
|
|
|
2014-04-22 16:57:47 +02:00
|
|
|
#undef OP_ENT
|
|
|
|
#undef INPUT
|
|
|
|
#undef OUTPUT
|
|
|
|
#undef END
|
|
|
|
#undef COND_REF
|
|
|
|
|
|
|
|
/* Operand instance lookup table. */
|
|
|
|
|
|
|
|
static const CGEN_OPINST *or1k_cgen_opinst_table[MAX_INSNS] = {
|
|
|
|
0,
|
|
|
|
& sfmt_l_j_ops[0],
|
or1k: Add the l.adrp insn and supporting relocations
This patch adds the new instruction and relocation as per proposal:
https://openrisc.io/proposals/ladrp
This is to be added to the spec in an upcoming revision. The new instruction
l.adrp loads the page offset of the current instruction offset by
a 21-bit immediate shifted left 13-bits. This is meant to be used with
a 13-bit lower bit page offset. This allows us to free up the got
register r16.
l.adrp r3, foo
l.ori r4, r3, po(foo)
l.lbz r5, po(foo)(r3)
l.sb po(foo)(r3), r6
The relocations we add are:
- BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry
asm: plta() implemented using l.ardp, meaning
no need for r16 (the GOT reg)
- BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address
asm: got()
- BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General
asm: tlsgd() Dynamic calculation
- BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local
asm: tlsldm() dynamic calculation
- BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial
asm: gottp() Executable calculation
- BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp
instructions)
- BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation
asm: po() i.e. mem loads, addi etc
- BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation
asm: po() i.e. mem stores, with split immediate
- BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs
asm: gotpo()
- BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs
asm: tlsgdpo()
- BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs
asm: tlsldmpo()
- BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs
asm: gottppo()
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* bfd-in2.h: Regenerated.
* elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for
R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21,
R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21,
R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13,
R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26.
(or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21,
BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26.
(elf_or1k_link_hash_table): Add field saw_plta.
(or1k_final_link_relocate): Add value calculations for new relocations.
(or1k_elf_relocate_section): Add section relocations for new
relocations.
(or1k_write_plt_entry): New function.
(or1k_elf_finish_dynamic_sections): Add support for PLTA relocations
using new l.adrp instruction. Cleanup PLT relocation code generation.
* libbfd.h: Regenerated.
* reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc (parse_disp26): Add support for plta() relocations.
(parse_disp21): New function.
(or1k_rclass): New enum.
(or1k_rtype): New enum.
(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
(parse_imm16): Add support for the new 21bit and 13bit relocations.
* or1korbis.cpu (f-disp26): Don't assume SI.
(f-disp21): New pc-relative 21-bit 13 shifted to right.
(insn-opcode): Add ADRP.
(l-adrp): New instruction.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
* testsuite/gas/or1k/allinsn.s: Add test for l.adrp.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
* testsuite/gas/or1k/reloc-1.s: Add tests to generate
R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13,
R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13
relocations.
* testsuite/gas/or1k/reloc-1.d: Add relocation results for
tests.
* testsuite/gas/or1k/reloc-2.s: Add negative tests for store to
gotpo().
* testsuite/gas/or1k/reloc-2.l: Add expected error test results.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/or1k.exp: Add test cases for plt generation.
* testsuite/ld-or1k/plt1.dd: New file.
* testsuite/ld-or1k/plt1.s: New file.
* testsuite/ld-or1k/plt1.x.dd: New file.
* testsuite/ld-or1k/plta1.dd: New file.
* testsuite/ld-or1k/plta1.s: New file.
* testsuite/ld-or1k/pltlib.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
R_OR1K_SLO13, R_OR1K_PLTA26.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerated.
* or1k-desc.c: Regenerated.
* or1k-desc.h: Regenerated.
* or1k-dis.c: Regenerated.
* or1k-ibld.c: Regenerated.
* or1k-opc.c: Regenerated.
* or1k-opc.h: Regenerated.
* or1k-opinst.c: Regenerated.
2018-10-05 04:41:41 +02:00
|
|
|
& sfmt_l_adrp_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_l_jal_ops[0],
|
|
|
|
& sfmt_l_jr_ops[0],
|
|
|
|
& sfmt_l_jalr_ops[0],
|
|
|
|
& sfmt_l_bnf_ops[0],
|
|
|
|
& sfmt_l_bnf_ops[0],
|
|
|
|
& sfmt_l_trap_ops[0],
|
|
|
|
& sfmt_l_trap_ops[0],
|
2014-07-20 19:26:09 +02:00
|
|
|
& sfmt_l_msync_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_l_nop_imm_ops[0],
|
2014-07-20 19:26:09 +02:00
|
|
|
& sfmt_l_msync_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_l_movhi_ops[0],
|
|
|
|
& sfmt_l_macrc_ops[0],
|
|
|
|
& sfmt_l_mfspr_ops[0],
|
|
|
|
& sfmt_l_mtspr_ops[0],
|
|
|
|
& sfmt_l_lwz_ops[0],
|
|
|
|
& sfmt_l_lws_ops[0],
|
2014-05-08 07:53:09 +02:00
|
|
|
& sfmt_l_lwa_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_l_lbz_ops[0],
|
|
|
|
& sfmt_l_lbs_ops[0],
|
|
|
|
& sfmt_l_lhz_ops[0],
|
|
|
|
& sfmt_l_lhs_ops[0],
|
|
|
|
& sfmt_l_sw_ops[0],
|
|
|
|
& sfmt_l_sb_ops[0],
|
|
|
|
& sfmt_l_sh_ops[0],
|
2014-05-08 07:53:09 +02:00
|
|
|
& sfmt_l_swa_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_l_sll_ops[0],
|
|
|
|
& sfmt_l_slli_ops[0],
|
|
|
|
& sfmt_l_sll_ops[0],
|
|
|
|
& sfmt_l_slli_ops[0],
|
|
|
|
& sfmt_l_sll_ops[0],
|
|
|
|
& sfmt_l_slli_ops[0],
|
|
|
|
& sfmt_l_sll_ops[0],
|
|
|
|
& sfmt_l_slli_ops[0],
|
|
|
|
& sfmt_l_and_ops[0],
|
|
|
|
& sfmt_l_and_ops[0],
|
|
|
|
& sfmt_l_and_ops[0],
|
|
|
|
& sfmt_l_add_ops[0],
|
|
|
|
& sfmt_l_add_ops[0],
|
|
|
|
& sfmt_l_addc_ops[0],
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
& sfmt_l_mul_ops[0],
|
|
|
|
& sfmt_l_muld_ops[0],
|
|
|
|
& sfmt_l_mulu_ops[0],
|
|
|
|
& sfmt_l_muld_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_l_div_ops[0],
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
& sfmt_l_divu_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_l_ff1_ops[0],
|
|
|
|
& sfmt_l_ff1_ops[0],
|
|
|
|
& sfmt_l_mfspr_ops[0],
|
|
|
|
& sfmt_l_mfspr_ops[0],
|
|
|
|
& sfmt_l_xori_ops[0],
|
|
|
|
& sfmt_l_addi_ops[0],
|
|
|
|
& sfmt_l_addic_ops[0],
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
& sfmt_l_muli_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_l_exths_ops[0],
|
|
|
|
& sfmt_l_exths_ops[0],
|
|
|
|
& sfmt_l_exths_ops[0],
|
|
|
|
& sfmt_l_exths_ops[0],
|
|
|
|
& sfmt_l_exths_ops[0],
|
|
|
|
& sfmt_l_exths_ops[0],
|
|
|
|
& sfmt_l_cmov_ops[0],
|
|
|
|
& sfmt_l_sfgts_ops[0],
|
|
|
|
& sfmt_l_sfgtsi_ops[0],
|
|
|
|
& sfmt_l_sfgts_ops[0],
|
|
|
|
& sfmt_l_sfgtsi_ops[0],
|
|
|
|
& sfmt_l_sfgts_ops[0],
|
|
|
|
& sfmt_l_sfgtsi_ops[0],
|
|
|
|
& sfmt_l_sfgts_ops[0],
|
|
|
|
& sfmt_l_sfgtsi_ops[0],
|
|
|
|
& sfmt_l_sfgts_ops[0],
|
|
|
|
& sfmt_l_sfgtsi_ops[0],
|
|
|
|
& sfmt_l_sfgts_ops[0],
|
|
|
|
& sfmt_l_sfgtsi_ops[0],
|
|
|
|
& sfmt_l_sfgts_ops[0],
|
|
|
|
& sfmt_l_sfgtsi_ops[0],
|
|
|
|
& sfmt_l_sfgts_ops[0],
|
|
|
|
& sfmt_l_sfgtsi_ops[0],
|
|
|
|
& sfmt_l_sfgts_ops[0],
|
|
|
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& sfmt_l_sfgtsi_ops[0],
|
|
|
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& sfmt_l_sfgts_ops[0],
|
|
|
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& sfmt_l_sfgtsi_ops[0],
|
|
|
|
& sfmt_l_mac_ops[0],
|
|
|
|
& sfmt_l_maci_ops[0],
|
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
2018-10-05 04:41:41 +02:00
|
|
|
& sfmt_l_macu_ops[0],
|
|
|
|
& sfmt_l_mac_ops[0],
|
|
|
|
& sfmt_l_macu_ops[0],
|
2014-07-20 19:26:09 +02:00
|
|
|
& sfmt_l_msync_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_lf_add_s_ops[0],
|
|
|
|
& sfmt_lf_add_d_ops[0],
|
2019-06-12 23:16:19 +02:00
|
|
|
& sfmt_lf_add_d32_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_lf_add_s_ops[0],
|
|
|
|
& sfmt_lf_add_d_ops[0],
|
2019-06-12 23:16:19 +02:00
|
|
|
& sfmt_lf_add_d32_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_lf_add_s_ops[0],
|
|
|
|
& sfmt_lf_add_d_ops[0],
|
2019-06-12 23:16:19 +02:00
|
|
|
& sfmt_lf_add_d32_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_lf_add_s_ops[0],
|
|
|
|
& sfmt_lf_add_d_ops[0],
|
2019-06-12 23:16:19 +02:00
|
|
|
& sfmt_lf_add_d32_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_lf_add_s_ops[0],
|
|
|
|
& sfmt_lf_add_d_ops[0],
|
2019-06-12 23:16:19 +02:00
|
|
|
& sfmt_lf_add_d32_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_lf_itof_s_ops[0],
|
|
|
|
& sfmt_lf_itof_d_ops[0],
|
2019-06-12 23:16:19 +02:00
|
|
|
& sfmt_lf_itof_d32_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_lf_ftoi_s_ops[0],
|
|
|
|
& sfmt_lf_ftoi_d_ops[0],
|
2019-06-12 23:16:19 +02:00
|
|
|
& sfmt_lf_ftoi_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
|
|
|
& sfmt_lf_sfeq_s_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d_ops[0],
|
|
|
|
& sfmt_lf_sfeq_d32_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
& sfmt_lf_madd_s_ops[0],
|
|
|
|
& sfmt_lf_madd_d_ops[0],
|
2019-06-12 23:16:19 +02:00
|
|
|
& sfmt_lf_madd_d32_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
2014-07-20 19:26:09 +02:00
|
|
|
& sfmt_l_msync_ops[0],
|
|
|
|
& sfmt_l_msync_ops[0],
|
2014-04-22 16:57:47 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* Function to call before using the operand instance table. */
|
|
|
|
|
|
|
|
void
|
2016-04-14 00:30:46 +02:00
|
|
|
or1k_cgen_init_opinst_table (CGEN_CPU_DESC cd)
|
2014-04-22 16:57:47 +02:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
const CGEN_OPINST **oi = & or1k_cgen_opinst_table[0];
|
|
|
|
CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries;
|
|
|
|
for (i = 0; i < MAX_INSNS; ++i)
|
|
|
|
insns[i].opinst = oi[i];
|
|
|
|
}
|