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tic4x: sign extension using shifts Don't do that. Especially don't use shift counts that assume the type being shifted is 32 bits when the type is long/unsigned long. Also reverts part of a change I made on 2019-12-11 to tic4x_print_register that on closer inspection turns out to be unnecessary. include/ * opcode/tic4x.h (EXTR): Delete. (EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign extension using shifts. Do trim INSERTU value to specified bitfield. opcodes/ * tic4x-dis.c (tic4x_print_register): Remove dead code. gas/ * config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap insertion.
2020-01-12 10:46:22 +01:00
2020-01-13 Alan Modra <amodra@gmail.com>
* tic4x-dis.c (tic4x_print_register): Remove dead code.
ubsan: fr30: left shift of negative value cpu/ * fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't left shift signed values. opcodes/ * fr30-ibld.c: Regenerate.
2020-01-11 03:02:11 +01:00
2020-01-13 Alan Modra <amodra@gmail.com>
* fr30-ibld.c: Regenerate.
ubsan: xgate: left shift of negative value * xgate-dis.c (print_insn): Don't left shift signed value. (ripBits): Formatting, use 1u.
2020-01-11 02:53:47 +01:00
2020-01-13 Alan Modra <amodra@gmail.com>
* xgate-dis.c (print_insn): Don't left shift signed value.
(ripBits): Formatting, use 1u.
ubsan: tilepro: signed integer overflow * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned. * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2020-01-09 22:57:33 +01:00
2020-01-10 Alan Modra <amodra@gmail.com>
* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
* tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
ubsan: m10300: shift exponent -4 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG, and XRREG value earlier to avoid a shift with negative exponent. * m10200-dis.c (disassemble): Similarly.
2020-01-08 21:29:42 +01:00
2020-01-10 Alan Modra <amodra@gmail.com>
* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
and XRREG value earlier to avoid a shift with negative exponent.
* m10200-dis.c (disassemble): Similarly.
Fix the cast used to prevent compile time warning about an always false test. PR 25224 * z80-dis.c (ld_ii_ii): Use correct cast.
2020-01-09 15:32:49 +01:00
2020-01-09 Nick Clifton <nickc@redhat.com>
PR 25224
* z80-dis.c (ld_ii_ii): Use correct cast.
Fix compile time warnings about comparisons always being false. PR 25224 gas * config/tc-z80.c (emit_ld_m_rr): Use integer types when checking opcode byte values. (emit_ld_r_r): Likewise. (emit_ld_rr_m): Likewise. (emit_ld_rr_nn): Likewise. opcodes * z80-dis.c (ld_ii_ii): Use character constant when checking opcode byte value.
2020-01-09 12:47:44 +01:00
2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 25224
* z80-dis.c (ld_ii_ii): Use character constant when checking
opcode byte value.
x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMD The disassembler change is such that in default mode we'd disassemble the insns (for there not ebing any conflicts), but when AMD64 mode was explicitly requested, we'd show them as "(bad)".
2020-01-09 11:38:01 +01:00
2020-01-09 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (SEP_Fixup): New.
(SEP): Define.
(dis386_twobyte): Use it for sysenter/sysexit.
(enum x86_64_isa): Change amd64 enumerator to value 1.
(OP_J): Compare isa64 against intel64 instead of amd64.
* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
forms.
* i386-tbl.h: Re-generate.
ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]' The fix is the additional ARRAY_SIZE test, the rest just tidies variable types rather than adding a cast to avoid warnings. opcodes/ * z8k-dis.c: Include libiberty.h (instr_data_s): Make max_fetched unsigned. (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. Don't exceed byte_info bounds. (output_instr): Make num_bytes unsigned. (unpack_instr): Likewise for nibl_count and loop. * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and idx unsigned. * z8k-opc.h: Regenerate. gas/ * config/tc-z8k.c (md_begin): Make idx unsigned. (get_specific): Likewise for this_index.
2020-01-08 02:12:36 +01:00
2020-01-08 Alan Modra <amodra@gmail.com>
* z8k-dis.c: Include libiberty.h
(instr_data_s): Make max_fetched unsigned.
(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
Don't exceed byte_info bounds.
(output_instr): Make num_bytes unsigned.
(unpack_instr): Likewise for nibl_count and loop.
* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
idx unsigned.
* z8k-opc.h: Regenerate.
[ARC] Add finer details for LLOCK and SCOND This patch changes the "class" of LLOCK/SCOND from "MEMORY" to "LLOCK/SCOND" respectively. Moreover, it corrects the "data_size_mode". These changes are necessary for GDB's atmoic sequence handler. Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
2020-01-07 14:25:15 +01:00
2020-01-07 Shahab Vahedi <shahab@synopsys.com>
* arc-tbl.h (llock): Use 'LLOCK' as class.
(llockd): Likewise.
(scond): Use 'SCOND' as class.
(scondd): Likewise.
(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
(scondd): Likewise.
ubsan: m32c: left shift of negative value There are probably a lot more of these still here. cpu/ * m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign bits before shifting rather than masking after shifting. (f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise. (f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise. (f-dsp-64-u16, f-dsp-8-s24): Likewise. (f-bitbase32-16-s19-unprefixed): Avoid signed left shift. opcodes/ * m32c-ibld.c: Regenerate.
2020-01-04 10:23:19 +01:00
2020-01-06 Alan Modra <amodra@gmail.com>
* m32c-ibld.c: Regenerate.
PR25344, z80 disassembler recursion PR 25344 * z80-dis.c (suffix): Don't use a local struct buffer copy. Peek at next byte to prevent recursion on repeated prefix bytes. Ensure uninitialised "mybuf" is not accessed. (print_insn_z80): Don't zero n_fetch and n_used here,.. (print_insn_z80_buf): ..do it here instead.
2020-01-05 23:22:39 +01:00
2020-01-06 Alan Modra <amodra@gmail.com>
PR 25344
* z80-dis.c (suffix): Don't use a local struct buffer copy.
Peek at next byte to prevent recursion on repeated prefix bytes.
Ensure uninitialised "mybuf" is not accessed.
(print_insn_z80): Don't zero n_fetch and n_used here,..
(print_insn_z80_buf): ..do it here instead.
ubsan: m32r: left shift of negative value cpu/ * m32r.cpu (f-disp8): Avoid left shift of negative values. (f-disp16, f-disp24): Likewise. opcodes/ * m32r-ibld.c: Regenerate.
2020-01-03 22:41:43 +01:00
2020-01-04 Alan Modra <amodra@gmail.com>
* m32r-ibld.c: Regenerate.
ubsan: cr16: left shift cannot be represented in type 'int' * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2020-01-02 22:42:00 +01:00
2020-01-04 Alan Modra <amodra@gmail.com>
* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
ubsan: crx: left shift cannot be represented in type 'int' * crx-dis.c (match_opcode): Avoid shift left of signed value.
2020-01-02 21:37:17 +01:00
2020-01-04 Alan Modra <amodra@gmail.com>
* crx-dis.c (match_opcode): Avoid shift left of signed value.
ubsan: d30v: left shift cannot be represented in type 'int' * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2020-01-01 09:16:43 +01:00
2020-01-04 Alan Modra <amodra@gmail.com>
* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
Arm64: correct {su,us}dot SIMD encodings According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
2020-01-03 10:14:16 +01:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
Arm64: correct address index operands for LD1RO{H,W,D} Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03 10:16:44 +01:00
* aarch64-tbl.h (aarch64_opcode_table): Use
SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2020-01-03 Jan Beulich <jbeulich@suse.com>
* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
Arm64: correct {su,us}dot SIMD encodings According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
2020-01-03 10:14:16 +01:00
forms of SUDOT and USDOT.
Arm64: correct uzp{1,2} mnemonics According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
2020-01-03 10:13:31 +01:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
Arm64: correct address index operands for LD1RO{H,W,D} Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03 10:16:44 +01:00
* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
Arm64: correct uzp{1,2} mnemonics According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
2020-01-03 10:13:31 +01:00
uzip{1,2}.
* opcodes/aarch64-dis-2.c: Re-generate.
Arm64: correct 64-bit element fmmla encoding There's just one bit of difference to the 32-bit element form, as per the documentation.
2020-01-03 10:12:49 +01:00
2020-01-03 Jan Beulich <jbeulich@suse.com>
Arm64: correct address index operands for LD1RO{H,W,D} Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03 10:16:44 +01:00
* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
Arm64: correct 64-bit element fmmla encoding There's just one bit of difference to the 32-bit element form, as per the documentation.
2020-01-03 10:12:49 +01:00
FMMLA encoding.
* opcodes/aarch64-dis-2.c: Re-generate.
Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02 15:10:40 +01:00
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
* z80-dis.c: Add support for eZ80 and Z80 instructions.
Re: Update year range in copyright notice of binutils files Add the ChangeLog entry.
2020-01-01 09:22:19 +01:00
2020-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2020-01-01 08:37:11 +01:00
For older changes see ChangeLog-2019
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
ChangeLog rotation
2020-01-01 08:37:11 +01:00
Copyright (C) 2020 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 11:44:31 +01:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
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