binutils-gdb/gdb/riscv-tdep.h

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/* Target-dependent header for the RISC-V architecture, for GDB, the
GNU Debugger.
Copyright (C) 2018-2019 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef RISCV_TDEP_H
#define RISCV_TDEP_H
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
#include "arch/riscv.h"
/* RiscV register numbers. */
enum
{
RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
RISCV_RA_REGNUM = 1, /* Return Address. */
RISCV_SP_REGNUM = 2, /* Stack Pointer. */
RISCV_GP_REGNUM = 3, /* Global Pointer. */
RISCV_TP_REGNUM = 4, /* Thread Pointer. */
RISCV_FP_REGNUM = 8, /* Frame Pointer. */
RISCV_A0_REGNUM = 10, /* First argument. */
RISCV_A1_REGNUM = 11, /* Second argument. */
RISCV_PC_REGNUM = 32, /* Program Counter. */
RISCV_NUM_INTEGER_REGS = 32,
RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
RISCV_FA0_REGNUM = 43,
RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
#define DECLARE_CSR(name, num) \
RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
RISCV_LAST_CSR_REGNUM = 4160,
RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
RISCV_PRIV_REGNUM = 4161,
RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
};
/* RiscV DWARF register numbers. */
enum
{
RISCV_DWARF_REGNUM_X0 = 0,
RISCV_DWARF_REGNUM_X31 = 31,
RISCV_DWARF_REGNUM_F0 = 32,
RISCV_DWARF_REGNUM_F31 = 63,
};
/* RISC-V specific per-architecture information. */
struct gdbarch_tdep
{
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
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/* Features about the target hardware that impact how the gdbarch is
configured. Two gdbarch instances are compatible only if this field
matches. */
struct riscv_gdbarch_features isa_features;
/* Features about the abi that impact how the gdbarch is configured. Two
gdbarch instances are compatible only if this field matches. */
struct riscv_gdbarch_features abi_features;
/* ISA-specific data types. */
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
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struct type *riscv_fpreg_d_type = nullptr;
};
/* Return the width in bytes of the general purpose registers for GDBARCH.
Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
RV128. */
extern int riscv_isa_xlen (struct gdbarch *gdbarch);
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
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/* Return the width in bytes of the hardware floating point registers for
GDBARCH. If this architecture has no floating point registers, then
return 0. Possible values are 4, 8, or 16 for depending on which of
single, double or quad floating point support is available. */
extern int riscv_isa_flen (struct gdbarch *gdbarch);
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
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/* Return the width in bytes of the general purpose register abi for
GDBARCH. This can be equal to, or less than RISCV_ISA_XLEN and reflects
how the binary was compiled rather than the hardware that is available.
It is possible that a binary compiled for RV32 is being run on an RV64
target, in which case the isa xlen is 8-bytes, and the abi xlen is
4-bytes. This will impact how inferior functions are called. */
extern int riscv_abi_xlen (struct gdbarch *gdbarch);
/* Return the width in bytes of the floating point register abi for
GDBARCH. This reflects how the binary was compiled rather than the
hardware that is available. It is possible that a binary is compiled
for single precision floating point, and then run on a target with
double precision floating point. A return value of 0 indicates that no
floating point abi is in use (floating point arguments will be passed
in integer registers) other possible return value are 4, 8, or 16 as
with RISCV_ISA_FLEN. */
extern int riscv_abi_flen (struct gdbarch *gdbarch);
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/* Single step based on where the current instruction will take us. */
extern std::vector<CORE_ADDR> riscv_software_single_step
(struct regcache *regcache);
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#endif /* RISCV_TDEP_H */