binutils-gdb/opcodes/tic30-dis.c

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/* Disassembly routines for TMS320C30 architecture
PR 14072 * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * alpha-opc.c: Include sysdep.h before any other header file. * alpha-dis.c: Likewise. * avr-dis.c: Likewise. * cgen-opc.c: Likewise. * cr16-dis.c: Likewise. * cris-dis.c: Likewise. * crx-dis.c: Likewise. * d10v-dis.c: Likewise. * d10v-opc.c: Likewise. * d30v-dis.c: Likewise. * d30v-opc.c: Likewise. * h8500-dis.c: Likewise. * i370-dis.c: Likewise. * i370-opc.c: Likewise. * m10200-dis.c: Likewise. * m10300-dis.c: Likewise. * micromips-opc.c: Likewise. * mips-opc.c: Likewise. * mips61-opc.c: Likewise. * moxie-dis.c: Likewise. * or32-opc.c: Likewise. * pj-dis.c: Likewise. * ppc-dis.c: Likewise. * ppc-opc.c: Likewise. * s390-dis.c: Likewise. * sh-dis.c: Likewise. * sh64-dis.c: Likewise. * sparc-dis.c: Likewise. * sparc-opc.c: Likewise. * spu-dis.c: Likewise. * tic30-dis.c: Likewise. * tic54x-dis.c: Likewise. * tic80-dis.c: Likewise. * tic80-opc.c: Likewise. * tilegx-dis.c: Likewise. * tilepro-dis.c: Likewise. * v850-dis.c: Likewise. * v850-opc.c: Likewise. * vax-dis.c: Likewise. * w65-dis.c: Likewise. * xgate-dis.c: Likewise. * xtensa-dis.c: Likewise. * rl78-decode.opc: Likewise. * rl78-decode.c: Regenerate. * rx-decode.opc: Likewise. * rx-decode.c: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in.h: Generate an error if included before config.h. * sysdep.h: Likewise. * bfd-in2.h: Regenerate. * compress.c: Remove #include "config.h". * plugin.c: Likewise. * elf32-m68hc1x.c: Include sysdep.h before alloca-conf.h. * elf64-hppa.c: Likewise. * som.c: Likewise. * xsymc.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * Makefile.am: Use wrappers around C files generated by flex. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * itbl-lex-wrapper.c: New file. * config/bfin-lex-wrapper.c: New file. * cgen.c: Include as.h before setjmp.h. * config/tc-dlx.c: Include as.h before any other header. * config/tc-h8300.c: Likewise. * config/tc-lm32.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-or32.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-xtensa.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * unwind-ia64.h: Include config.h.
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Copyright 1998, 1999, 2000, 2002, 2005, 2007, 2009, 2012
2009-09-02 09:25:43 +02:00
Free Software Foundation, Inc.
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Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
2007-07-05 11:49:03 +02:00
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
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PR 14072 * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * alpha-opc.c: Include sysdep.h before any other header file. * alpha-dis.c: Likewise. * avr-dis.c: Likewise. * cgen-opc.c: Likewise. * cr16-dis.c: Likewise. * cris-dis.c: Likewise. * crx-dis.c: Likewise. * d10v-dis.c: Likewise. * d10v-opc.c: Likewise. * d30v-dis.c: Likewise. * d30v-opc.c: Likewise. * h8500-dis.c: Likewise. * i370-dis.c: Likewise. * i370-opc.c: Likewise. * m10200-dis.c: Likewise. * m10300-dis.c: Likewise. * micromips-opc.c: Likewise. * mips-opc.c: Likewise. * mips61-opc.c: Likewise. * moxie-dis.c: Likewise. * or32-opc.c: Likewise. * pj-dis.c: Likewise. * ppc-dis.c: Likewise. * ppc-opc.c: Likewise. * s390-dis.c: Likewise. * sh-dis.c: Likewise. * sh64-dis.c: Likewise. * sparc-dis.c: Likewise. * sparc-opc.c: Likewise. * spu-dis.c: Likewise. * tic30-dis.c: Likewise. * tic54x-dis.c: Likewise. * tic80-dis.c: Likewise. * tic80-opc.c: Likewise. * tilegx-dis.c: Likewise. * tilepro-dis.c: Likewise. * v850-dis.c: Likewise. * v850-opc.c: Likewise. * vax-dis.c: Likewise. * w65-dis.c: Likewise. * xgate-dis.c: Likewise. * xtensa-dis.c: Likewise. * rl78-decode.opc: Likewise. * rl78-decode.c: Regenerate. * rx-decode.opc: Likewise. * rx-decode.c: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in.h: Generate an error if included before config.h. * sysdep.h: Likewise. * bfd-in2.h: Regenerate. * compress.c: Remove #include "config.h". * plugin.c: Likewise. * elf32-m68hc1x.c: Include sysdep.h before alloca-conf.h. * elf64-hppa.c: Likewise. * som.c: Likewise. * xsymc.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * Makefile.am: Use wrappers around C files generated by flex. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * itbl-lex-wrapper.c: New file. * config/bfin-lex-wrapper.c: New file. * cgen.c: Include as.h before setjmp.h. * config/tc-dlx.c: Include as.h before any other header. * config/tc-h8300.c: Likewise. * config/tc-lm32.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-or32.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-xtensa.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * unwind-ia64.h: Include config.h.
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#include "sysdep.h"
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#include <errno.h>
#include <math.h>
#include "dis-asm.h"
#include "opcode/tic30.h"
#define NORMAL_INSN 1
#define PARALLEL_INSN 2
/* Gets the type of instruction based on the top 2 or 3 bits of the
instruction word. */
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#define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
/* Instruction types. */
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#define TWO_OPERAND_1 0x00000000
#define TWO_OPERAND_2 0x40000000
#define THREE_OPERAND 0x20000000
#define PAR_STORE 0xC0000000
#define MUL_ADDS 0x80000000
#define BRANCHES 0x60000000
/* Specific instruction id bits. */
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#define NORMAL_IDEN 0x1F800000
#define PAR_STORE_IDEN 0x3E000000
#define MUL_ADD_IDEN 0x2C000000
#define BR_IMM_IDEN 0x1F000000
#define BR_COND_IDEN 0x1C3F0000
/* Addressing modes. */
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#define AM_REGISTER 0x00000000
#define AM_DIRECT 0x00200000
#define AM_INDIRECT 0x00400000
#define AM_IMM 0x00600000
#define P_FIELD 0x03000000
#define REG_AR0 0x08
#define LDP_INSN 0x08700000
/* TMS320C30 program counter for current instruction. */
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static unsigned int _pc;
struct instruction
{
int type;
Updated sources to avoid using the identifier name "new", which is a keyword in c++. * bfd/aoutx.h (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol. * bfd/coffgen.c (coff_make_empty_symbol) (coff_bfd_make_debug_symbol): Rename variable new to new_symbol. * bfd/cpu-ia64-opc.c (ext_reg, ins_imms_scaled): Rename variable new to new_insn. * bfd/doc/chew.c (newentry, add_intrinsic): Rename variable new to new_d. * bfd/ecoff.c (_bfd_ecoff_make_empty_symbol): Rename variable new to new_symbol. * bfd/elf32-m68k.c (elf_m68k_get_got_entry_type): Rename argument new to new_reloc. * bfd/hash.c (bfd_hash_lookup): Rename variable new to new_string. * bfd/ieee.c (ieee_make_empty_symbol): Rename variable new to new_symbol. * bfd/linker.c (bfd_new_link_order): Rename variable new to new_lo. * bfd/mach-o.c (bfd_mach_o_sizeof_headers): Rename variable new to symbol. * bfd/oasys.c (oasys_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/pdp11.c (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol_type. * bfd/plugin.c (bfd_plugin_make_empty_symbol): Rename variable new to new_symbol. * bfd/rs6000-core.c (CoreHdr, VmInfo): Rename union member new to new_dump. (read_hdr, rs6000coff_core_p) (rs6000coff_core_file_matches_executable_p) (rs6000coff_core_file_failing_command) (rs6000coff_core_file_failing_signal): Updated function to use new union member name. * bfd/som.c (som_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/syms.c (_bfd_generic_make_empty_symbol): Rename variable new to new_symbol. * bfd/tekhex.c (first_phase, tekhex_make_empty_symbol): Rename variable new to new_symbol. * binutils/nlmconv.c (main): Rename variable new to new_name. * gas/config/tc-arm.c (insert_reg_alias): Rename variable new to new_reg. * gas/config/tc-dlx.c (parse_operand): Rename variable new to new_pos. * gas/config/tc-ia64.c (ia64_gen_real_reloc_type): Rename variable new to newr. * gas/config/tc-mcore.c (parse_exp, parse_imm): Rename variable new to new_pointer. * gas/config/tc-microblaze.c (parse_exp, parse_imm, check_got): Change name from new to new_pointer. * gas/config/tc-or32.c (parse_operand): Rename variable new to new_pointer. * gas/config/tc-pdp11.c (md_assemble): Rename variable new to new_pointer. * gas/config/tc-pj.c (alias): Change argument new to new_name. * gas/config/tc-score.c (s3_build_score_ops_hsh): Rename variable new to new_opcode. (s3_build_dependency_insn_hsh) Rename variable new to new_i2n. (s3_convert): Rename variables old and new to r_old and r_new. * gas/config/tc-score7.c (s7_build_score_ops_hsh): Rename variable new to new_opcode. (s7_build_dependency_insn_hsh): Rename variable new to new_i2d. (s7_b32_relax_to_b16, s7_convert_frag): Rename variables old and new to r_old and r_new. * gas/config/tc-sh.c (parse_exp): Rename variable new to new_pointer. * gas/config/tc-sh64.c (shmedia_parse_exp): Rename variable new to new_pointer. * gas/config/tc-tic4x.c (tic4x_operand_parse): Rename variable new to new_pointer. * gas/config/tc-z8k.c (parse_exp): Rename variable new to new_pointer. * gas/listing.c (listing_newline): Rename variable new to new_i. * ld/ldexp.c (exp_intop, exp_bigintop, exp_relop, exp_binop) (exp_trinop, exp_unop, exp_nameop, exp_assop): Rename variable new to new_e. * ld/ldfile.c (ldfile_add_library_path): Rename variable new to new_dirs. (ldfile_add_arch): Rename variable new to new_arch. * ld/ldlang.c (new_statement, lang_final, lang_add_wild) (lang_target, lang_add_fill, lang_add_data, lang_add_assignment) (lang_add_insert): Rename variable new to new_stmt. (new_afile): Added missing cast. (lang_memory_region_lookup): Rename variable new to new_region. (init_os): Rename variable new to new_userdata. (lang_add_section): Rename variable new to new_section. (ldlang_add_undef): Rename variable new to new_undef. (realsymbol): Rename variable new to new_name. * opcodes/z8kgen.c (internal, gas): Rename variable new to new_op. Updated sources to avoid using the identifier name "template", which is a keyword in c++. * bfd/elf32-arm.c (struct stub_def): Rename member template to template_sequence. (arm_build_one_stub, find_stub_size_and_template, arm_size_one_stub, arm_map_one_stub): Rename variable template to template_sequence. * bfd/elfxx-ia64.c (elfNN_ia64_relax_br, elfNN_ia64_relax_brl): Rename variable template to template_val. * gas/config/tc-arm.c (struct asm_cond, struct asm_psr, struct asm_barrier_opt): Change member template to template_name. (md_begin): Update code to reflect new member names. * gas/config/tc-i386.c (struct templates, struct _i386_insn) (match_template, cpu_flags_match, match_reg_size, match_mem_size) (operand_size_match, md_begin, i386_print_statistics, pi) (build_vex_prefix, md_assemble, parse_insn, optimize_imm) (optimize_disp): Updated code to use new names. (parse_insn): Added casts. * gas/config/tc-ia64.c (dot_template, emit_one_bundle): Updated code to use new names. * gas/config/tc-score.c (struct s3_asm_opcode): Renamed member template to template_name. (s3_parse_16_32_inst, s3_parse_48_inst, s3_do_macro_ldst_label, s3_build_score_ops_hsh): Update code to use new names. * gas/config/tc-score7.c (struct s7_asm_opcode): Renamed member template to template_name. (s7_parse_16_32_inst, s7_do_macro_ldst_label, s7_build_score_ops_hsh): Update code to use new names. * gas/config/tc-tic30.c (md_begin, struct tic30_insn) (md_assemble): Update code to use new names. * gas/config/tc-tic54x.c (struct _tic54x_insn, md_begin) (optimize_insn, tic54x_parse_insn, next_line_shows_parallel): Update code to use new names. * include/opcode/tic30.h (template): Rename type template to insn_template. Updated code to use new name. * include/opcode/tic54x.h (template): Rename type template to insn_template. * opcodes/cris-dis.c (bytes_to_skip): Update code to use new name. * opcodes/i386-dis.c (putop): Update code to use new name. * opcodes/i386-gen.c (process_i386_opcodes): Update code to use new name. * opcodes/i386-opc.h (struct template): Rename struct template to insn_template. Update code accordingly. * opcodes/i386-tbl.h (i386_optab): Update type to use new name. * opcodes/ia64-dis.c (print_insn_ia64): Rename variable template to template_val. * opcodes/tic30-dis.c (struct instruction, get_tic30_instruction): Update code to use new name. * opcodes/tic54x-dis.c (has_lkaddr, get_insn_size) (print_parallel_instruction, print_insn_tic54x, tic54x_get_insn): Update code to use new name. * opcodes/tic54x-opc.c (tic54x_unknown_opcode, tic54x_optab): Update type to new name.
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insn_template *tm;
partemplate *ptm;
};
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static int
get_tic30_instruction (unsigned long insn_word, struct instruction *insn)
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{
switch (GET_TYPE (insn_word))
{
case TWO_OPERAND_1:
case TWO_OPERAND_2:
case THREE_OPERAND:
insn->type = NORMAL_INSN;
{
Updated sources to avoid using the identifier name "new", which is a keyword in c++. * bfd/aoutx.h (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol. * bfd/coffgen.c (coff_make_empty_symbol) (coff_bfd_make_debug_symbol): Rename variable new to new_symbol. * bfd/cpu-ia64-opc.c (ext_reg, ins_imms_scaled): Rename variable new to new_insn. * bfd/doc/chew.c (newentry, add_intrinsic): Rename variable new to new_d. * bfd/ecoff.c (_bfd_ecoff_make_empty_symbol): Rename variable new to new_symbol. * bfd/elf32-m68k.c (elf_m68k_get_got_entry_type): Rename argument new to new_reloc. * bfd/hash.c (bfd_hash_lookup): Rename variable new to new_string. * bfd/ieee.c (ieee_make_empty_symbol): Rename variable new to new_symbol. * bfd/linker.c (bfd_new_link_order): Rename variable new to new_lo. * bfd/mach-o.c (bfd_mach_o_sizeof_headers): Rename variable new to symbol. * bfd/oasys.c (oasys_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/pdp11.c (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol_type. * bfd/plugin.c (bfd_plugin_make_empty_symbol): Rename variable new to new_symbol. * bfd/rs6000-core.c (CoreHdr, VmInfo): Rename union member new to new_dump. (read_hdr, rs6000coff_core_p) (rs6000coff_core_file_matches_executable_p) (rs6000coff_core_file_failing_command) (rs6000coff_core_file_failing_signal): Updated function to use new union member name. * bfd/som.c (som_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/syms.c (_bfd_generic_make_empty_symbol): Rename variable new to new_symbol. * bfd/tekhex.c (first_phase, tekhex_make_empty_symbol): Rename variable new to new_symbol. * binutils/nlmconv.c (main): Rename variable new to new_name. * gas/config/tc-arm.c (insert_reg_alias): Rename variable new to new_reg. * gas/config/tc-dlx.c (parse_operand): Rename variable new to new_pos. * gas/config/tc-ia64.c (ia64_gen_real_reloc_type): Rename variable new to newr. * gas/config/tc-mcore.c (parse_exp, parse_imm): Rename variable new to new_pointer. * gas/config/tc-microblaze.c (parse_exp, parse_imm, check_got): Change name from new to new_pointer. * gas/config/tc-or32.c (parse_operand): Rename variable new to new_pointer. * gas/config/tc-pdp11.c (md_assemble): Rename variable new to new_pointer. * gas/config/tc-pj.c (alias): Change argument new to new_name. * gas/config/tc-score.c (s3_build_score_ops_hsh): Rename variable new to new_opcode. (s3_build_dependency_insn_hsh) Rename variable new to new_i2n. (s3_convert): Rename variables old and new to r_old and r_new. * gas/config/tc-score7.c (s7_build_score_ops_hsh): Rename variable new to new_opcode. (s7_build_dependency_insn_hsh): Rename variable new to new_i2d. (s7_b32_relax_to_b16, s7_convert_frag): Rename variables old and new to r_old and r_new. * gas/config/tc-sh.c (parse_exp): Rename variable new to new_pointer. * gas/config/tc-sh64.c (shmedia_parse_exp): Rename variable new to new_pointer. * gas/config/tc-tic4x.c (tic4x_operand_parse): Rename variable new to new_pointer. * gas/config/tc-z8k.c (parse_exp): Rename variable new to new_pointer. * gas/listing.c (listing_newline): Rename variable new to new_i. * ld/ldexp.c (exp_intop, exp_bigintop, exp_relop, exp_binop) (exp_trinop, exp_unop, exp_nameop, exp_assop): Rename variable new to new_e. * ld/ldfile.c (ldfile_add_library_path): Rename variable new to new_dirs. (ldfile_add_arch): Rename variable new to new_arch. * ld/ldlang.c (new_statement, lang_final, lang_add_wild) (lang_target, lang_add_fill, lang_add_data, lang_add_assignment) (lang_add_insert): Rename variable new to new_stmt. (new_afile): Added missing cast. (lang_memory_region_lookup): Rename variable new to new_region. (init_os): Rename variable new to new_userdata. (lang_add_section): Rename variable new to new_section. (ldlang_add_undef): Rename variable new to new_undef. (realsymbol): Rename variable new to new_name. * opcodes/z8kgen.c (internal, gas): Rename variable new to new_op. Updated sources to avoid using the identifier name "template", which is a keyword in c++. * bfd/elf32-arm.c (struct stub_def): Rename member template to template_sequence. (arm_build_one_stub, find_stub_size_and_template, arm_size_one_stub, arm_map_one_stub): Rename variable template to template_sequence. * bfd/elfxx-ia64.c (elfNN_ia64_relax_br, elfNN_ia64_relax_brl): Rename variable template to template_val. * gas/config/tc-arm.c (struct asm_cond, struct asm_psr, struct asm_barrier_opt): Change member template to template_name. (md_begin): Update code to reflect new member names. * gas/config/tc-i386.c (struct templates, struct _i386_insn) (match_template, cpu_flags_match, match_reg_size, match_mem_size) (operand_size_match, md_begin, i386_print_statistics, pi) (build_vex_prefix, md_assemble, parse_insn, optimize_imm) (optimize_disp): Updated code to use new names. (parse_insn): Added casts. * gas/config/tc-ia64.c (dot_template, emit_one_bundle): Updated code to use new names. * gas/config/tc-score.c (struct s3_asm_opcode): Renamed member template to template_name. (s3_parse_16_32_inst, s3_parse_48_inst, s3_do_macro_ldst_label, s3_build_score_ops_hsh): Update code to use new names. * gas/config/tc-score7.c (struct s7_asm_opcode): Renamed member template to template_name. (s7_parse_16_32_inst, s7_do_macro_ldst_label, s7_build_score_ops_hsh): Update code to use new names. * gas/config/tc-tic30.c (md_begin, struct tic30_insn) (md_assemble): Update code to use new names. * gas/config/tc-tic54x.c (struct _tic54x_insn, md_begin) (optimize_insn, tic54x_parse_insn, next_line_shows_parallel): Update code to use new names. * include/opcode/tic30.h (template): Rename type template to insn_template. Updated code to use new name. * include/opcode/tic54x.h (template): Rename type template to insn_template. * opcodes/cris-dis.c (bytes_to_skip): Update code to use new name. * opcodes/i386-dis.c (putop): Update code to use new name. * opcodes/i386-gen.c (process_i386_opcodes): Update code to use new name. * opcodes/i386-opc.h (struct template): Rename struct template to insn_template. Update code accordingly. * opcodes/i386-tbl.h (i386_optab): Update type to use new name. * opcodes/ia64-dis.c (print_insn_ia64): Rename variable template to template_val. * opcodes/tic30-dis.c (struct instruction, get_tic30_instruction): Update code to use new name. * opcodes/tic54x-dis.c (has_lkaddr, get_insn_size) (print_parallel_instruction, print_insn_tic54x, tic54x_get_insn): Update code to use new name. * opcodes/tic54x-opc.c (tic54x_unknown_opcode, tic54x_optab): Update type to new name.
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insn_template *current_optab = (insn_template *) tic30_optab;
1999-05-03 09:29:11 +02:00
for (; current_optab < tic30_optab_end; current_optab++)
{
if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
{
if (current_optab->operands == 0)
{
if (current_optab->base_opcode == insn_word)
{
insn->tm = current_optab;
break;
}
}
else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN))
{
insn->tm = current_optab;
break;
}
}
}
}
break;
1999-05-03 09:29:11 +02:00
case PAR_STORE:
insn->type = PARALLEL_INSN;
{
partemplate *current_optab = (partemplate *) tic30_paroptab;
1999-05-03 09:29:11 +02:00
for (; current_optab < tic30_paroptab_end; current_optab++)
{
if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
{
if ((current_optab->base_opcode & PAR_STORE_IDEN)
== (insn_word & PAR_STORE_IDEN))
1999-05-03 09:29:11 +02:00
{
insn->ptm = current_optab;
break;
}
}
}
}
break;
1999-05-03 09:29:11 +02:00
case MUL_ADDS:
insn->type = PARALLEL_INSN;
{
partemplate *current_optab = (partemplate *) tic30_paroptab;
1999-05-03 09:29:11 +02:00
for (; current_optab < tic30_paroptab_end; current_optab++)
{
if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
{
if ((current_optab->base_opcode & MUL_ADD_IDEN)
== (insn_word & MUL_ADD_IDEN))
1999-05-03 09:29:11 +02:00
{
insn->ptm = current_optab;
break;
}
}
}
}
break;
1999-05-03 09:29:11 +02:00
case BRANCHES:
insn->type = NORMAL_INSN;
{
Updated sources to avoid using the identifier name "new", which is a keyword in c++. * bfd/aoutx.h (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol. * bfd/coffgen.c (coff_make_empty_symbol) (coff_bfd_make_debug_symbol): Rename variable new to new_symbol. * bfd/cpu-ia64-opc.c (ext_reg, ins_imms_scaled): Rename variable new to new_insn. * bfd/doc/chew.c (newentry, add_intrinsic): Rename variable new to new_d. * bfd/ecoff.c (_bfd_ecoff_make_empty_symbol): Rename variable new to new_symbol. * bfd/elf32-m68k.c (elf_m68k_get_got_entry_type): Rename argument new to new_reloc. * bfd/hash.c (bfd_hash_lookup): Rename variable new to new_string. * bfd/ieee.c (ieee_make_empty_symbol): Rename variable new to new_symbol. * bfd/linker.c (bfd_new_link_order): Rename variable new to new_lo. * bfd/mach-o.c (bfd_mach_o_sizeof_headers): Rename variable new to symbol. * bfd/oasys.c (oasys_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/pdp11.c (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol_type. * bfd/plugin.c (bfd_plugin_make_empty_symbol): Rename variable new to new_symbol. * bfd/rs6000-core.c (CoreHdr, VmInfo): Rename union member new to new_dump. (read_hdr, rs6000coff_core_p) (rs6000coff_core_file_matches_executable_p) (rs6000coff_core_file_failing_command) (rs6000coff_core_file_failing_signal): Updated function to use new union member name. * bfd/som.c (som_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/syms.c (_bfd_generic_make_empty_symbol): Rename variable new to new_symbol. * bfd/tekhex.c (first_phase, tekhex_make_empty_symbol): Rename variable new to new_symbol. * binutils/nlmconv.c (main): Rename variable new to new_name. * gas/config/tc-arm.c (insert_reg_alias): Rename variable new to new_reg. * gas/config/tc-dlx.c (parse_operand): Rename variable new to new_pos. * gas/config/tc-ia64.c (ia64_gen_real_reloc_type): Rename variable new to newr. * gas/config/tc-mcore.c (parse_exp, parse_imm): Rename variable new to new_pointer. * gas/config/tc-microblaze.c (parse_exp, parse_imm, check_got): Change name from new to new_pointer. * gas/config/tc-or32.c (parse_operand): Rename variable new to new_pointer. * gas/config/tc-pdp11.c (md_assemble): Rename variable new to new_pointer. * gas/config/tc-pj.c (alias): Change argument new to new_name. * gas/config/tc-score.c (s3_build_score_ops_hsh): Rename variable new to new_opcode. (s3_build_dependency_insn_hsh) Rename variable new to new_i2n. (s3_convert): Rename variables old and new to r_old and r_new. * gas/config/tc-score7.c (s7_build_score_ops_hsh): Rename variable new to new_opcode. (s7_build_dependency_insn_hsh): Rename variable new to new_i2d. (s7_b32_relax_to_b16, s7_convert_frag): Rename variables old and new to r_old and r_new. * gas/config/tc-sh.c (parse_exp): Rename variable new to new_pointer. * gas/config/tc-sh64.c (shmedia_parse_exp): Rename variable new to new_pointer. * gas/config/tc-tic4x.c (tic4x_operand_parse): Rename variable new to new_pointer. * gas/config/tc-z8k.c (parse_exp): Rename variable new to new_pointer. * gas/listing.c (listing_newline): Rename variable new to new_i. * ld/ldexp.c (exp_intop, exp_bigintop, exp_relop, exp_binop) (exp_trinop, exp_unop, exp_nameop, exp_assop): Rename variable new to new_e. * ld/ldfile.c (ldfile_add_library_path): Rename variable new to new_dirs. (ldfile_add_arch): Rename variable new to new_arch. * ld/ldlang.c (new_statement, lang_final, lang_add_wild) (lang_target, lang_add_fill, lang_add_data, lang_add_assignment) (lang_add_insert): Rename variable new to new_stmt. (new_afile): Added missing cast. (lang_memory_region_lookup): Rename variable new to new_region. (init_os): Rename variable new to new_userdata. (lang_add_section): Rename variable new to new_section. (ldlang_add_undef): Rename variable new to new_undef. (realsymbol): Rename variable new to new_name. * opcodes/z8kgen.c (internal, gas): Rename variable new to new_op. Updated sources to avoid using the identifier name "template", which is a keyword in c++. * bfd/elf32-arm.c (struct stub_def): Rename member template to template_sequence. (arm_build_one_stub, find_stub_size_and_template, arm_size_one_stub, arm_map_one_stub): Rename variable template to template_sequence. * bfd/elfxx-ia64.c (elfNN_ia64_relax_br, elfNN_ia64_relax_brl): Rename variable template to template_val. * gas/config/tc-arm.c (struct asm_cond, struct asm_psr, struct asm_barrier_opt): Change member template to template_name. (md_begin): Update code to reflect new member names. * gas/config/tc-i386.c (struct templates, struct _i386_insn) (match_template, cpu_flags_match, match_reg_size, match_mem_size) (operand_size_match, md_begin, i386_print_statistics, pi) (build_vex_prefix, md_assemble, parse_insn, optimize_imm) (optimize_disp): Updated code to use new names. (parse_insn): Added casts. * gas/config/tc-ia64.c (dot_template, emit_one_bundle): Updated code to use new names. * gas/config/tc-score.c (struct s3_asm_opcode): Renamed member template to template_name. (s3_parse_16_32_inst, s3_parse_48_inst, s3_do_macro_ldst_label, s3_build_score_ops_hsh): Update code to use new names. * gas/config/tc-score7.c (struct s7_asm_opcode): Renamed member template to template_name. (s7_parse_16_32_inst, s7_do_macro_ldst_label, s7_build_score_ops_hsh): Update code to use new names. * gas/config/tc-tic30.c (md_begin, struct tic30_insn) (md_assemble): Update code to use new names. * gas/config/tc-tic54x.c (struct _tic54x_insn, md_begin) (optimize_insn, tic54x_parse_insn, next_line_shows_parallel): Update code to use new names. * include/opcode/tic30.h (template): Rename type template to insn_template. Updated code to use new name. * include/opcode/tic54x.h (template): Rename type template to insn_template. * opcodes/cris-dis.c (bytes_to_skip): Update code to use new name. * opcodes/i386-dis.c (putop): Update code to use new name. * opcodes/i386-gen.c (process_i386_opcodes): Update code to use new name. * opcodes/i386-opc.h (struct template): Rename struct template to insn_template. Update code accordingly. * opcodes/i386-tbl.h (i386_optab): Update type to use new name. * opcodes/ia64-dis.c (print_insn_ia64): Rename variable template to template_val. * opcodes/tic30-dis.c (struct instruction, get_tic30_instruction): Update code to use new name. * opcodes/tic54x-dis.c (has_lkaddr, get_insn_size) (print_parallel_instruction, print_insn_tic54x, tic54x_get_insn): Update code to use new name. * opcodes/tic54x-opc.c (tic54x_unknown_opcode, tic54x_optab): Update type to new name.
2009-08-30 00:11:02 +02:00
insn_template *current_optab = (insn_template *) tic30_optab;
1999-05-03 09:29:11 +02:00
for (; current_optab < tic30_optab_end; current_optab++)
{
if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
{
if (current_optab->operand_types[0] & Imm24)
{
if ((current_optab->base_opcode & BR_IMM_IDEN)
== (insn_word & BR_IMM_IDEN))
1999-05-03 09:29:11 +02:00
{
insn->tm = current_optab;
break;
}
}
else if (current_optab->operands > 0)
{
if ((current_optab->base_opcode & BR_COND_IDEN)
== (insn_word & BR_COND_IDEN))
1999-05-03 09:29:11 +02:00
{
insn->tm = current_optab;
break;
}
}
else
{
if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000))
== (insn_word & (BR_COND_IDEN | 0x00800000)))
1999-05-03 09:29:11 +02:00
{
insn->tm = current_optab;
break;
}
}
}
}
}
break;
default:
return 0;
}
return 1;
}
static int
get_register_operand (unsigned char fragment, char *buffer)
{
const reg *current_reg = tic30_regtab;
if (buffer == NULL)
return 0;
for (; current_reg < tic30_regtab_end; current_reg++)
{
if ((fragment & 0x1F) == current_reg->opcode)
{
strcpy (buffer, current_reg->name);
return 1;
}
}
return 0;
}
static int
get_indirect_operand (unsigned short fragment,
int size,
char *buffer)
{
unsigned char mod;
unsigned arnum;
unsigned char disp;
if (buffer == NULL)
return 0;
/* Determine which bits identify the sections of the indirect
operand based on the size in bytes. */
switch (size)
{
case 1:
mod = (fragment & 0x00F8) >> 3;
arnum = (fragment & 0x0007);
disp = 0;
break;
case 2:
mod = (fragment & 0xF800) >> 11;
arnum = (fragment & 0x0700) >> 8;
disp = (fragment & 0x00FF);
break;
default:
return 0;
}
{
const ind_addr_type *current_ind = tic30_indaddr_tab;
for (; current_ind < tic30_indaddrtab_end; current_ind++)
{
if (current_ind->modfield == mod)
{
if (current_ind->displacement == IMPLIED_DISP && size == 2)
continue;
else
{
size_t i, len;
int bufcnt;
len = strlen (current_ind->syntax);
for (i = 0, bufcnt = 0; i < len; i++, bufcnt++)
{
buffer[bufcnt] = current_ind->syntax[i];
if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r')
buffer[++bufcnt] = arnum + '0';
if (buffer[bufcnt] == '('
&& current_ind->displacement == DISP_REQUIRED)
{
sprintf (&buffer[bufcnt + 1], "%u", disp);
bufcnt += strlen (&buffer[bufcnt + 1]);
}
}
buffer[bufcnt + 1] = '\0';
break;
}
}
}
}
return 1;
}
static int
cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat)
{
unsigned long exponent, sign, mant;
union
{
unsigned long l;
float f;
} val;
if (size == 2)
{
if ((tmsfloat & 0x0000F000) == 0x00008000)
tmsfloat = 0x80000000;
else
{
tmsfloat <<= 16;
tmsfloat = (long) tmsfloat >> 4;
}
}
exponent = tmsfloat & 0xFF000000;
if (exponent == 0x80000000)
{
*ieeefloat = 0.0;
return 1;
}
exponent += 0x7F000000;
sign = (tmsfloat & 0x00800000) << 8;
mant = tmsfloat & 0x007FFFFF;
if (exponent == 0xFF000000)
{
if (mant == 0)
*ieeefloat = ERANGE;
#ifdef HUGE_VALF
if (sign == 0)
*ieeefloat = HUGE_VALF;
else
*ieeefloat = -HUGE_VALF;
#else
if (sign == 0)
*ieeefloat = 1.0 / 0.0;
else
*ieeefloat = -1.0 / 0.0;
#endif
return 1;
}
exponent >>= 1;
if (sign)
{
mant = (~mant) & 0x007FFFFF;
mant += 1;
exponent += mant & 0x00800000;
exponent &= 0x7F800000;
mant &= 0x007FFFFF;
}
if (tmsfloat == 0x80000000)
sign = mant = exponent = 0;
tmsfloat = sign | exponent | mant;
val.l = tmsfloat;
*ieeefloat = val.f;
return 1;
}
static int
print_two_operand (disassemble_info *info,
unsigned long insn_word,
struct instruction *insn)
1999-05-03 09:29:11 +02:00
{
char name[12];
char operand[2][13] =
{
{0},
{0}
};
1999-05-03 09:29:11 +02:00
float f_number;
if (insn->tm == NULL)
return 0;
strcpy (name, insn->tm->name);
if (insn->tm->opcode_modifier == AddressMode)
{
int src_op, dest_op;
/* Determine whether instruction is a store or a normal instruction. */
if ((insn->tm->operand_types[1] & (Direct | Indirect))
== (Direct | Indirect))
1999-05-03 09:29:11 +02:00
{
src_op = 1;
dest_op = 0;
}
else
{
src_op = 0;
dest_op = 1;
}
/* Get the destination register. */
1999-05-03 09:29:11 +02:00
if (insn->tm->operands == 2)
get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]);
/* Get the source operand based on addressing mode. */
1999-05-03 09:29:11 +02:00
switch (insn_word & AddressMode)
{
case AM_REGISTER:
/* Check for the NOP instruction before getting the operand. */
1999-05-03 09:29:11 +02:00
if ((insn->tm->operand_types[0] & NotReq) == 0)
get_register_operand ((insn_word & 0x0000001F), operand[src_op]);
break;
case AM_DIRECT:
sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF));
break;
case AM_INDIRECT:
get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]);
break;
case AM_IMM:
/* Get the value of the immediate operand based on variable type. */
1999-05-03 09:29:11 +02:00
switch (insn->tm->imm_arg_type)
{
case Imm_Float:
cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number);
sprintf (operand[src_op], "%2.2f", f_number);
break;
case Imm_SInt:
sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF));
break;
case Imm_UInt:
sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF));
break;
default:
return 0;
}
/* Handle special case for LDP instruction. */
1999-05-03 09:29:11 +02:00
if ((insn_word & 0xFFFFFF00) == LDP_INSN)
{
strcpy (name, "ldp");
sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16);
operand[1][0] = '\0';
}
}
}
/* Handle case for stack and rotate instructions. */
1999-05-03 09:29:11 +02:00
else if (insn->tm->operands == 1)
{
if (insn->tm->opcode_modifier == StackOp)
get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]);
1999-05-03 09:29:11 +02:00
}
/* Output instruction to stream. */
1999-05-03 09:29:11 +02:00
info->fprintf_func (info->stream, " %s %s%c%s", name,
operand[0][0] ? operand[0] : "",
operand[1][0] ? ',' : ' ',
operand[1][0] ? operand[1] : "");
return 1;
}
static int
print_three_operand (disassemble_info *info,
unsigned long insn_word,
struct instruction *insn)
1999-05-03 09:29:11 +02:00
{
char operand[3][13] =
{
{0},
{0},
{0}
};
1999-05-03 09:29:11 +02:00
if (insn->tm == NULL)
return 0;
switch (insn_word & AddressMode)
{
case AM_REGISTER:
get_register_operand ((insn_word & 0x000000FF), operand[0]);
get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
break;
case AM_DIRECT:
get_register_operand ((insn_word & 0x000000FF), operand[0]);
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
break;
case AM_INDIRECT:
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
break;
case AM_IMM:
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
break;
default:
return 0;
}
if (insn->tm->operands == 3)
get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]);
info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name,
operand[0], operand[1],
operand[2][0] ? ',' : ' ',
operand[2][0] ? operand[2] : "");
return 1;
}
static int
print_par_insn (disassemble_info *info,
unsigned long insn_word,
struct instruction *insn)
1999-05-03 09:29:11 +02:00
{
size_t i, len;
char *name1, *name2;
char operand[2][3][13] =
{
{
{0},
{0},
{0}
},
1999-05-03 09:29:11 +02:00
{
{0},
{0},
{0}
}
};
1999-05-03 09:29:11 +02:00
if (insn->ptm == NULL)
return 0;
/* Parse out the names of each of the parallel instructions from the
q_insn1_insn2 format. */
1999-05-03 09:29:11 +02:00
name1 = (char *) strdup (insn->ptm->name + 2);
name2 = "";
len = strlen (name1);
for (i = 0; i < len; i++)
{
if (name1[i] == '_')
{
name2 = &name1[i + 1];
name1[i] = '\0';
break;
}
}
/* Get the operands of the instruction based on the operand order. */
1999-05-03 09:29:11 +02:00
switch (insn->ptm->oporder)
{
case OO_4op1:
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
break;
case OO_4op2:
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]);
get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
break;
case OO_4op3:
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]);
break;
case OO_5op1:
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
break;
case OO_5op2:
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
break;
case OO_PField:
if (insn_word & 0x00800000)
get_register_operand (0x01, operand[0][2]);
else
get_register_operand (0x00, operand[0][2]);
if (insn_word & 0x00400000)
get_register_operand (0x03, operand[1][2]);
else
get_register_operand (0x02, operand[1][2]);
switch (insn_word & P_FIELD)
{
case 0x00000000:
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]);
break;
case 0x01000000:
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]);
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
break;
case 0x02000000:
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]);
get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
break;
case 0x03000000:
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
break;
}
break;
default:
return 0;
}
info->fprintf_func (info->stream, " %s %s,%s%c%s", name1,
operand[0][0], operand[0][1],
operand[0][2][0] ? ',' : ' ',
operand[0][2][0] ? operand[0][2] : "");
info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2,
operand[1][0], operand[1][1],
operand[1][2][0] ? ',' : ' ',
operand[1][2][0] ? operand[1][2] : "");
free (name1);
return 1;
}
static int
print_branch (disassemble_info *info,
unsigned long insn_word,
struct instruction *insn)
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{
char operand[2][13] =
{
{0},
{0}
};
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unsigned long address;
int print_label = 0;
if (insn->tm == NULL)
return 0;
/* Get the operands for 24-bit immediate jumps. */
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if (insn->tm->operand_types[0] & Imm24)
{
address = insn_word & 0x00FFFFFF;
sprintf (operand[0], "0x%lX", address);
print_label = 1;
}
/* Get the operand for the trap instruction. */
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else if (insn->tm->operand_types[0] & IVector)
{
address = insn_word & 0x0000001F;
sprintf (operand[0], "0x%lX", address);
}
else
{
address = insn_word & 0x0000FFFF;
/* Get the operands for the DB instructions. */
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if (insn->tm->operands == 2)
{
get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]);
if (insn_word & PCRel)
{
sprintf (operand[1], "%d", (short) address);
print_label = 1;
}
else
get_register_operand (insn_word & 0x0000001F, operand[1]);
}
/* Get the operands for the standard branches. */
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else if (insn->tm->operands == 1)
{
if (insn_word & PCRel)
{
address = (short) address;
sprintf (operand[0], "%ld", address);
print_label = 1;
}
else
get_register_operand (insn_word & 0x0000001F, operand[0]);
}
}
info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name,
operand[0][0] ? operand[0] : "",
operand[1][0] ? ',' : ' ',
operand[1][0] ? operand[1] : "");
/* Print destination of branch in relation to current symbol. */
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if (print_label && info->symbols)
{
asymbol *sym = *info->symbols;
if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel))
{
address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4);
/* Check for delayed instruction, if so adjust destination. */
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if (insn_word & 0x00200000)
address += 2;
}
else
{
address -= ((sym->section->vma + sym->value) / 4);
}
if (address == 0)
info->fprintf_func (info->stream, " <%s>", sym->name);
else
info->fprintf_func (info->stream, " <%s %c %d>", sym->name,
((short) address < 0) ? '-' : '+',
abs (address));
}
return 1;
}
int
print_insn_tic30 (bfd_vma pc, disassemble_info *info)
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{
unsigned long insn_word;
struct instruction insn = { 0, NULL, NULL };
bfd_vma bufaddr = pc - info->buffer_vma;
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/* Obtain the current instruction word from the buffer. */
insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) |
(*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3);
_pc = pc / 4;
/* Get the instruction refered to by the current instruction word
and print it out based on its type. */
if (!get_tic30_instruction (insn_word, &insn))
return -1;
switch (GET_TYPE (insn_word))
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{
case TWO_OPERAND_1:
case TWO_OPERAND_2:
if (!print_two_operand (info, insn_word, &insn))
return -1;
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break;
case THREE_OPERAND:
if (!print_three_operand (info, insn_word, &insn))
return -1;
break;
case PAR_STORE:
case MUL_ADDS:
if (!print_par_insn (info, insn_word, &insn))
return -1;
break;
case BRANCHES:
if (!print_branch (info, insn_word, &insn))
return -1;
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break;
}
return 4;
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}