2012-08-13 16:52:54 +02:00
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/* aarch64-gen.c -- Generate tables and routines for opcode lookup and
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instruction encoding and decoding.
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2020-01-01 08:57:01 +01:00
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Copyright (C) 2012-2020 Free Software Foundation, Inc.
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2012-08-13 16:52:54 +02:00
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Contributed by ARM Ltd.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#include "sysdep.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdarg.h>
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#include "libiberty.h"
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#include "getopt.h"
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#include "opcode/aarch64.h"
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2016-05-03 12:48:56 +02:00
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#define VERIFIER(x) NULL
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2012-08-13 16:52:54 +02:00
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#include "aarch64-tbl.h"
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static int debug = 0;
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/* Structure used in the decoding tree to group a list of aarch64_opcode
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entries. */
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struct opcode_node
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{
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aarch64_insn opcode;
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aarch64_insn mask;
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/* Index of the entry in the original table; the top 2 bits help
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determine the table. */
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unsigned int index;
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struct opcode_node *next;
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};
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typedef struct opcode_node opcode_node;
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/* Head of the list of the opcode_node after read_table. */
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static opcode_node opcode_nodes_head;
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/* Node in the decoding tree. */
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struct bittree
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{
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unsigned int bitno;
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/* 0, 1, and X (don't care). */
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struct bittree *bits[2];
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/* List of opcodes; only valid for the leaf node. */
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opcode_node *list;
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};
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/* Allocate and initialize an opcode_node. */
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static opcode_node*
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new_opcode_node (void)
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{
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opcode_node* ent = malloc (sizeof (opcode_node));
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if (!ent)
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abort ();
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ent->opcode = 0;
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ent->mask = 0;
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ent->index = -1;
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ent->next = NULL;
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return ent;
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}
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/* Multiple tables are supported, although currently only one table is
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in use. N.B. there are still some functions have the table name
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'aarch64_opcode_table' hard-coded in, e.g. print_find_next_opcode;
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therefore some amount of work needs to be done if the full support
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for multiple tables needs to be enabled. */
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static const struct aarch64_opcode *aarch64_opcode_tables[] =
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{aarch64_opcode_table};
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/* Use top 2 bits to indiate which table. */
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static unsigned int
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initialize_index (const struct aarch64_opcode* table)
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{
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int i;
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const int num_of_tables = sizeof (aarch64_opcode_tables)
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/ sizeof (struct aarch64_opcode *);
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for (i = 0; i < num_of_tables; ++i)
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if (table == aarch64_opcode_tables [i])
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break;
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if (i == num_of_tables)
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abort ();
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return (unsigned int)i << 30;
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}
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static inline const struct aarch64_opcode *
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index2table (unsigned int index)
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{
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return aarch64_opcode_tables[(index >> 30) & 0x3];
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}
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static inline unsigned int
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real_index (unsigned int index)
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{
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return index & ((1 << 30) - 1);
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}
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/* Given OPCODE_NODE, return the corresponding aarch64_opcode*. */
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static const aarch64_opcode*
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get_aarch64_opcode (const opcode_node *opcode_node)
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{
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if (opcode_node == NULL)
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return NULL;
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return &index2table (opcode_node->index)[real_index (opcode_node->index)];
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}
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static void
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read_table (const struct aarch64_opcode* table)
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{
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const struct aarch64_opcode *ent = table;
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opcode_node **new_ent;
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unsigned int index = initialize_index (table);
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if (!ent->name)
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return;
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new_ent = &opcode_nodes_head.next;
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while (*new_ent)
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new_ent = &(*new_ent)->next;
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do
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{
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/* F_PSEUDO needs to be used together with F_ALIAS to indicate an alias
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opcode is a programmer friendly pseudo instruction available only in
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the assembly code (thus will not show up in the disassembly). */
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2017-05-18 07:17:40 +02:00
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assert (!pseudo_opcode_p (ent) || alias_opcode_p (ent));
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2012-08-13 16:52:54 +02:00
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/* Skip alias (inc. pseudo) opcode. */
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2017-05-18 07:17:40 +02:00
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if (alias_opcode_p (ent))
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2012-08-13 16:52:54 +02:00
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{
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index++;
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continue;
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}
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*new_ent = new_opcode_node ();
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(*new_ent)->opcode = ent->opcode;
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(*new_ent)->mask = ent->mask;
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(*new_ent)->index = index++;
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new_ent = &((*new_ent)->next);
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} while ((++ent)->name);
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}
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static inline void
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print_one_opcode_node (opcode_node* ent)
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{
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printf ("%s\t%08x\t%08x\t%d\n", get_aarch64_opcode (ent)->name,
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get_aarch64_opcode (ent)->opcode, get_aarch64_opcode (ent)->mask,
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(int)real_index (ent->index));
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}
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/* As an internal debugging utility, print out the list of nodes pointed
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by opcode_nodes_head. */
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static void
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print_opcode_nodes (void)
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{
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opcode_node* ent = opcode_nodes_head.next;
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printf ("print_opcode_nodes table:\n");
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while (ent)
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{
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print_one_opcode_node (ent);
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ent = ent->next;
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}
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}
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static struct bittree*
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new_bittree_node (void)
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{
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struct bittree* node;
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node = malloc (sizeof (struct bittree));
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if (!node)
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abort ();
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node->bitno = -1;
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node->bits[0] = NULL;
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node->bits[1] = NULL;
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return node;
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}
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/* The largest number of opcode entries that exist at a leaf node of the
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decoding decision tree. The reason that there can be more than one
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opcode entry is because some opcodes have shared field that is partially
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constrained and thus cannot be fully isolated using the algorithm
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here. */
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static int max_num_opcodes_at_leaf_node = 0;
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/* Given a list of opcodes headed by *OPCODE, try to establish one bit that
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is shared by all the opcodes in the list as one of base opcode bits. If
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such a bit is found, divide the list of the opcodes into two based on the
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value of the bit.
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Store the bit number in BITTREE->BITNO if the division succeeds. If unable
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to determine such a bit or there is only one opcode in the list, the list
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is decided to be undividable and OPCODE will be assigned to BITTREE->LIST.
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The function recursively call itself until OPCODE is undividable.
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2015-08-12 13:45:07 +02:00
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2012-08-13 16:52:54 +02:00
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N.B. the nature of this algrithm determines that given any value in the
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32-bit space, the computed decision tree will always be able to find one or
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more opcodes entries for it, regardless whether there is a valid instruction
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defined for this value or not. In order to detect the undefined values,
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when the caller obtains the opcode entry/entries, it should at least compare
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the bit-wise AND result of the value and the mask with the base opcode
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value; if the two are different, it means that the value is undefined
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(although the value may be still undefined when the comparison is the same,
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in which case call aarch64_opcode_decode to carry out further checks). */
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static void
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divide_table_1 (struct bittree *bittree, opcode_node *opcode)
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{
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aarch64_insn mask_and;
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opcode_node *ent;
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unsigned int bitno;
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aarch64_insn bitmask;
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opcode_node list0, list1, **ptr0, **ptr1;
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static int depth = 0;
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++depth;
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if (debug)
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printf ("Enter into depth %d\n", depth);
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assert (opcode != NULL);
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/* Succeed when there is only one opcode left. */
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if (!opcode->next)
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{
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if (debug)
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{
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printf ("opcode isolated:\n");
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print_one_opcode_node (opcode);
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}
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goto divide_table_1_finish;
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}
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2020-02-25 06:04:46 +01:00
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divide_table_1_try_again:
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2012-08-13 16:52:54 +02:00
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mask_and = -1;
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ent = opcode;
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while (ent)
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{
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mask_and &= ent->mask;
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ent = ent->next;
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}
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if (debug)
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printf ("mask and result: %08x\n", (unsigned int)mask_and);
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/* If no more bit to look into, we have to accept the reality then. */
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if (!mask_and)
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{
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int i;
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opcode_node *ptr;
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if (debug)
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{
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ptr = opcode;
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printf ("Isolated opcode group:\n");
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do {
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print_one_opcode_node (ptr);
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ptr = ptr->next;
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} while (ptr);
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}
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/* Count the number of opcodes. */
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for (i = 0, ptr = opcode; ptr; ++i)
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ptr = ptr->next;
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if (i > max_num_opcodes_at_leaf_node)
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max_num_opcodes_at_leaf_node = i;
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goto divide_table_1_finish;
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}
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/* Pick up the right most bit that is 1. */
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bitno = 0;
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while (!(mask_and & (1 << bitno)))
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++bitno;
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bitmask = (1 << bitno);
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if (debug)
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printf ("use bit %d\n", bitno);
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/* Record in the bittree. */
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bittree->bitno = bitno;
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/* Get two new opcode lists; adjust their masks. */
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list0.next = NULL;
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list1.next = NULL;
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ptr0 = &list0.next;
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ptr1 = &list1.next;
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ent = opcode;
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while (ent)
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{
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if (ent->opcode & bitmask)
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{
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ent->mask &= (~bitmask);
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*ptr1 = ent;
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ent = ent->next;
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(*ptr1)->next = NULL;
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ptr1 = &(*ptr1)->next;
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}
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else
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{
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ent->mask &= (~bitmask);
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*ptr0 = ent;
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ent = ent->next;
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(*ptr0)->next = NULL;
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ptr0 = &(*ptr0)->next;
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}
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}
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/* If BITNO can NOT divide the opcode group, try next bit. */
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if (list0.next == NULL)
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{
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opcode = list1.next;
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goto divide_table_1_try_again;
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}
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else if (list1.next == NULL)
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{
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|
|
|
opcode = list0.next;
|
|
|
|
|
goto divide_table_1_try_again;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Further divide. */
|
|
|
|
|
bittree->bits[0] = new_bittree_node ();
|
|
|
|
|
bittree->bits[1] = new_bittree_node ();
|
|
|
|
|
divide_table_1 (bittree->bits[0], list0.next);
|
|
|
|
|
divide_table_1 (bittree->bits[1], list1.next);
|
|
|
|
|
|
2020-02-25 06:04:46 +01:00
|
|
|
|
divide_table_1_finish:
|
2012-08-13 16:52:54 +02:00
|
|
|
|
if (debug)
|
|
|
|
|
printf ("Leave from depth %d\n", depth);
|
|
|
|
|
--depth;
|
|
|
|
|
|
|
|
|
|
/* Record the opcode entries on this leaf node. */
|
|
|
|
|
bittree->list = opcode;
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Call divide_table_1 to divide the all the opcodes and thus create the
|
|
|
|
|
decoding decision tree. */
|
|
|
|
|
static struct bittree *
|
|
|
|
|
divide_table (void)
|
|
|
|
|
{
|
|
|
|
|
struct bittree *bittree = new_bittree_node ();
|
|
|
|
|
divide_table_1 (bittree, opcode_nodes_head.next);
|
|
|
|
|
return bittree;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Read in all of the tables, create the decoding decision tree and return
|
|
|
|
|
the tree root. */
|
|
|
|
|
static struct bittree *
|
|
|
|
|
initialize_decoder_tree (void)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
const int num_of_tables = (sizeof (aarch64_opcode_tables)
|
|
|
|
|
/ sizeof (struct aarch64_opcode *));
|
|
|
|
|
for (i = 0; i < num_of_tables; ++i)
|
|
|
|
|
read_table (aarch64_opcode_tables [i]);
|
|
|
|
|
if (debug)
|
|
|
|
|
print_opcode_nodes ();
|
|
|
|
|
return divide_table ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __attribute__ ((format (printf, 2, 3)))
|
|
|
|
|
indented_print (unsigned int indent, const char *format, ...)
|
|
|
|
|
{
|
|
|
|
|
va_list ap;
|
|
|
|
|
va_start (ap, format);
|
2016-09-21 17:48:06 +02:00
|
|
|
|
printf ("%*s", (int) indent, "");
|
2012-08-13 16:52:54 +02:00
|
|
|
|
vprintf (format, ap);
|
|
|
|
|
va_end (ap);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* N.B. read the comment above divide_table_1 for the reason why the generated
|
|
|
|
|
decision tree function never returns NULL. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_decision_tree_1 (unsigned int indent, struct bittree* bittree)
|
|
|
|
|
{
|
|
|
|
|
/* PATTERN is only used to generate comment in the code. */
|
|
|
|
|
static char pattern[33] = "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx";
|
2017-07-24 12:26:58 +02:00
|
|
|
|
/* Low bits in PATTERN will be printed first which then look as the high
|
|
|
|
|
bits in comment. We need to reverse the index to get correct print. */
|
|
|
|
|
unsigned int msb = sizeof (pattern) - 2;
|
2012-08-13 16:52:54 +02:00
|
|
|
|
assert (bittree != NULL);
|
|
|
|
|
|
|
|
|
|
/* Leaf node located. */
|
|
|
|
|
if (bittree->bits[0] == NULL && bittree->bits[1] == NULL)
|
|
|
|
|
{
|
|
|
|
|
assert (bittree->list != NULL);
|
|
|
|
|
indented_print (indent, "/* 33222222222211111111110000000000\n");
|
|
|
|
|
indented_print (indent, " 10987654321098765432109876543210\n");
|
|
|
|
|
indented_print (indent, " %s\n", pattern);
|
|
|
|
|
indented_print (indent, " %s. */\n",
|
|
|
|
|
get_aarch64_opcode (bittree->list)->name);
|
|
|
|
|
indented_print (indent, "return %u;\n",
|
|
|
|
|
real_index (bittree->list->index));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Walk down the decoder tree. */
|
|
|
|
|
indented_print (indent, "if (((word >> %d) & 0x1) == 0)\n", bittree->bitno);
|
|
|
|
|
indented_print (indent, " {\n");
|
2017-07-24 12:26:58 +02:00
|
|
|
|
pattern[msb - bittree->bitno] = '0';
|
2012-08-13 16:52:54 +02:00
|
|
|
|
print_decision_tree_1 (indent + 4, bittree->bits[0]);
|
|
|
|
|
indented_print (indent, " }\n");
|
|
|
|
|
indented_print (indent, "else\n");
|
|
|
|
|
indented_print (indent, " {\n");
|
2017-07-24 12:26:58 +02:00
|
|
|
|
pattern[msb - bittree->bitno] = '1';
|
2012-08-13 16:52:54 +02:00
|
|
|
|
print_decision_tree_1 (indent + 4, bittree->bits[1]);
|
|
|
|
|
indented_print (indent, " }\n");
|
2017-07-24 12:26:58 +02:00
|
|
|
|
pattern[msb - bittree->bitno] = 'x';
|
2012-08-13 16:52:54 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Generate aarch64_opcode_lookup in C code to the standard output. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_decision_tree (struct bittree* bittree)
|
|
|
|
|
{
|
|
|
|
|
if (debug)
|
|
|
|
|
printf ("Enter print_decision_tree\n");
|
|
|
|
|
|
|
|
|
|
printf ("/* Called by aarch64_opcode_lookup. */\n\n");
|
|
|
|
|
|
|
|
|
|
printf ("static int\n");
|
|
|
|
|
printf ("aarch64_opcode_lookup_1 (uint32_t word)\n");
|
|
|
|
|
printf ("{\n");
|
|
|
|
|
|
|
|
|
|
print_decision_tree_1 (2, bittree);
|
|
|
|
|
|
|
|
|
|
printf ("}\n\n");
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
printf ("/* Lookup opcode WORD in the opcode table. N.B. all alias\n");
|
|
|
|
|
printf (" opcodes are ignored here. */\n\n");
|
|
|
|
|
|
|
|
|
|
printf ("const aarch64_opcode *\n");
|
|
|
|
|
printf ("aarch64_opcode_lookup (uint32_t word)\n");
|
|
|
|
|
printf ("{\n");
|
|
|
|
|
printf (" return aarch64_opcode_table + aarch64_opcode_lookup_1 (word);\n");
|
|
|
|
|
printf ("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_find_next_opcode_1 (struct bittree* bittree)
|
|
|
|
|
{
|
|
|
|
|
assert (bittree != NULL);
|
|
|
|
|
|
|
|
|
|
/* Leaf node located. */
|
|
|
|
|
if (bittree->bits[0] == NULL && bittree->bits[1] == NULL)
|
|
|
|
|
{
|
|
|
|
|
assert (bittree->list != NULL);
|
|
|
|
|
/* Find multiple opcode entries in one leaf node. */
|
|
|
|
|
if (bittree->list->next != NULL)
|
|
|
|
|
{
|
|
|
|
|
opcode_node *list = bittree->list;
|
|
|
|
|
while (list != NULL)
|
|
|
|
|
{
|
|
|
|
|
const aarch64_opcode *curr = get_aarch64_opcode (list);
|
|
|
|
|
const aarch64_opcode *next = get_aarch64_opcode (list->next);
|
|
|
|
|
|
|
|
|
|
printf (" case %u: ",
|
|
|
|
|
(unsigned int)(curr - aarch64_opcode_table));
|
|
|
|
|
if (list->next != NULL)
|
|
|
|
|
{
|
|
|
|
|
printf ("value = %u; break;\t", real_index (list->next->index));
|
|
|
|
|
printf ("/* %s --> %s. */\n", curr->name, next->name);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
printf ("return NULL;\t\t");
|
|
|
|
|
printf ("/* %s --> NULL. */\n", curr->name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
list = list->next;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Walk down the decoder tree. */
|
|
|
|
|
print_find_next_opcode_1 (bittree->bits[0]);
|
|
|
|
|
print_find_next_opcode_1 (bittree->bits[1]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Generate aarch64_find_next_opcode in C code to the standard output. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_find_next_opcode (struct bittree* bittree)
|
|
|
|
|
{
|
|
|
|
|
if (debug)
|
|
|
|
|
printf ("Enter print_find_next_opcode\n");
|
|
|
|
|
|
|
|
|
|
printf ("\n");
|
|
|
|
|
printf ("const aarch64_opcode *\n");
|
|
|
|
|
printf ("aarch64_find_next_opcode (const aarch64_opcode *opcode)\n");
|
|
|
|
|
printf ("{\n");
|
|
|
|
|
printf (" /* Use the index as the key to locate the next opcode. */\n");
|
|
|
|
|
printf (" int key = opcode - aarch64_opcode_table;\n");
|
|
|
|
|
printf (" int value;\n");
|
|
|
|
|
printf (" switch (key)\n");
|
|
|
|
|
printf (" {\n");
|
|
|
|
|
|
|
|
|
|
print_find_next_opcode_1 (bittree);
|
|
|
|
|
|
|
|
|
|
printf (" default: return NULL;\n");
|
|
|
|
|
printf (" }\n\n");
|
|
|
|
|
|
|
|
|
|
printf (" return aarch64_opcode_table + value;\n");
|
|
|
|
|
printf ("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Release the dynamic memory resource allocated for the generation of the
|
|
|
|
|
decoder tree. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
release_resource_decoder_tree (struct bittree* bittree)
|
|
|
|
|
{
|
|
|
|
|
assert (bittree != NULL);
|
|
|
|
|
|
|
|
|
|
/* Leaf node located. */
|
|
|
|
|
if (bittree->bits[0] == NULL && bittree->bits[1] == NULL)
|
|
|
|
|
{
|
|
|
|
|
assert (bittree->list != NULL);
|
|
|
|
|
/* Free opcode_nodes. */
|
|
|
|
|
opcode_node *list = bittree->list;
|
|
|
|
|
while (list != NULL)
|
|
|
|
|
{
|
|
|
|
|
opcode_node *next = list->next;
|
|
|
|
|
free (list);
|
|
|
|
|
list = next;
|
|
|
|
|
}
|
|
|
|
|
/* Free the tree node. */
|
|
|
|
|
free (bittree);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Walk down the decoder tree. */
|
|
|
|
|
release_resource_decoder_tree (bittree->bits[0]);
|
|
|
|
|
release_resource_decoder_tree (bittree->bits[1]);
|
|
|
|
|
|
|
|
|
|
/* Free the tree node. */
|
|
|
|
|
free (bittree);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Generate aarch64_find_real_opcode in C code to the standard output.
|
|
|
|
|
TABLE points to the alias info table, while NUM indicates the number of
|
|
|
|
|
entries in the table. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_find_real_opcode (const opcode_node *table, int num)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
|
printf ("Enter print_find_real_opcode\n");
|
|
|
|
|
|
|
|
|
|
printf ("\n");
|
|
|
|
|
printf ("const aarch64_opcode *\n");
|
|
|
|
|
printf ("aarch64_find_real_opcode (const aarch64_opcode *opcode)\n");
|
|
|
|
|
printf ("{\n");
|
|
|
|
|
printf (" /* Use the index as the key to locate the real opcode. */\n");
|
|
|
|
|
printf (" int key = opcode - aarch64_opcode_table;\n");
|
|
|
|
|
printf (" int value;\n");
|
|
|
|
|
printf (" switch (key)\n");
|
|
|
|
|
printf (" {\n");
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < num; ++i)
|
|
|
|
|
{
|
|
|
|
|
const opcode_node *real = table + i;
|
|
|
|
|
const opcode_node *alias = real->next;
|
|
|
|
|
for (; alias; alias = alias->next)
|
|
|
|
|
printf (" case %u:\t/* %s */\n", real_index (alias->index),
|
|
|
|
|
get_aarch64_opcode (alias)->name);
|
|
|
|
|
printf (" value = %u;\t/* --> %s. */\n", real_index (real->index),
|
|
|
|
|
get_aarch64_opcode (real)->name);
|
|
|
|
|
printf (" break;\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
printf (" default: return NULL;\n");
|
|
|
|
|
printf (" }\n\n");
|
|
|
|
|
|
|
|
|
|
printf (" return aarch64_opcode_table + value;\n");
|
|
|
|
|
printf ("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Generate aarch64_find_alias_opcode in C code to the standard output.
|
|
|
|
|
TABLE points to the alias info table, while NUM indicates the number of
|
|
|
|
|
entries in the table. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_find_alias_opcode (const opcode_node *table, int num)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
|
printf ("Enter print_find_alias_opcode\n");
|
|
|
|
|
|
|
|
|
|
printf ("\n");
|
|
|
|
|
printf ("const aarch64_opcode *\n");
|
|
|
|
|
printf ("aarch64_find_alias_opcode (const aarch64_opcode *opcode)\n");
|
|
|
|
|
printf ("{\n");
|
|
|
|
|
printf (" /* Use the index as the key to locate the alias opcode. */\n");
|
|
|
|
|
printf (" int key = opcode - aarch64_opcode_table;\n");
|
|
|
|
|
printf (" int value;\n");
|
|
|
|
|
printf (" switch (key)\n");
|
|
|
|
|
printf (" {\n");
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < num; ++i)
|
|
|
|
|
{
|
|
|
|
|
const opcode_node *node = table + i;
|
|
|
|
|
assert (node->next);
|
|
|
|
|
printf (" case %u: value = %u; break;", real_index (node->index),
|
|
|
|
|
real_index (node->next->index));
|
|
|
|
|
printf ("\t/* %s --> %s. */\n", get_aarch64_opcode (node)->name,
|
|
|
|
|
get_aarch64_opcode (node->next)->name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
printf (" default: return NULL;\n");
|
|
|
|
|
printf (" }\n\n");
|
|
|
|
|
|
|
|
|
|
printf (" return aarch64_opcode_table + value;\n");
|
|
|
|
|
printf ("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Generate aarch64_find_next_alias_opcode in C code to the standard output.
|
|
|
|
|
TABLE points to the alias info table, while NUM indicates the number of
|
|
|
|
|
entries in the table. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_find_next_alias_opcode (const opcode_node *table, int num)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
|
printf ("Enter print_find_next_alias_opcode\n");
|
|
|
|
|
|
|
|
|
|
printf ("\n");
|
|
|
|
|
printf ("const aarch64_opcode *\n");
|
|
|
|
|
printf ("aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)\n");
|
|
|
|
|
printf ("{\n");
|
|
|
|
|
printf (" /* Use the index as the key to locate the next opcode. */\n");
|
|
|
|
|
printf (" int key = opcode - aarch64_opcode_table;\n");
|
|
|
|
|
printf (" int value;\n");
|
|
|
|
|
printf (" switch (key)\n");
|
|
|
|
|
printf (" {\n");
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < num; ++i)
|
|
|
|
|
{
|
|
|
|
|
const opcode_node *node = table + i;
|
|
|
|
|
assert (node->next);
|
|
|
|
|
if (node->next->next == NULL)
|
|
|
|
|
continue;
|
|
|
|
|
while (node->next->next)
|
|
|
|
|
{
|
|
|
|
|
printf (" case %u: value = %u; break;", real_index (node->next->index),
|
|
|
|
|
real_index (node->next->next->index));
|
|
|
|
|
printf ("\t/* %s --> %s. */\n",
|
|
|
|
|
get_aarch64_opcode (node->next)->name,
|
|
|
|
|
get_aarch64_opcode (node->next->next)->name);
|
|
|
|
|
node = node->next;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
printf (" default: return NULL;\n");
|
|
|
|
|
printf (" }\n\n");
|
|
|
|
|
|
|
|
|
|
printf (" return aarch64_opcode_table + value;\n");
|
|
|
|
|
printf ("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Given OPCODE, establish and return a link list of alias nodes in the
|
|
|
|
|
preferred order. */
|
|
|
|
|
|
|
|
|
|
opcode_node *
|
|
|
|
|
find_alias_opcode (const aarch64_opcode *opcode)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
2016-11-11 11:22:56 +01:00
|
|
|
|
/* Assume maximum of 32 disassemble preference candidates. */
|
|
|
|
|
const int max_num_aliases = 32;
|
2012-08-13 16:52:54 +02:00
|
|
|
|
const aarch64_opcode *ent;
|
2015-11-27 16:02:26 +01:00
|
|
|
|
const aarch64_opcode *preferred[max_num_aliases + 1];
|
2012-08-13 16:52:54 +02:00
|
|
|
|
opcode_node head, **next;
|
|
|
|
|
|
|
|
|
|
assert (opcode_has_alias (opcode));
|
|
|
|
|
|
|
|
|
|
i = 0;
|
2015-11-27 16:02:26 +01:00
|
|
|
|
if (opcode->name != NULL)
|
|
|
|
|
preferred[i++] = opcode;
|
2012-08-13 16:52:54 +02:00
|
|
|
|
ent = aarch64_opcode_table;
|
|
|
|
|
while (ent->name != NULL)
|
|
|
|
|
{
|
|
|
|
|
/* The mask of an alias opcode must be equal to or a super-set (i.e.
|
|
|
|
|
more constrained) of that of the aliased opcode; so is the base
|
|
|
|
|
opcode value. */
|
2017-05-18 07:17:40 +02:00
|
|
|
|
if (alias_opcode_p (ent)
|
2012-08-13 16:52:54 +02:00
|
|
|
|
&& (ent->mask & opcode->mask) == opcode->mask
|
|
|
|
|
&& (opcode->mask & ent->opcode) == (opcode->mask & opcode->opcode))
|
|
|
|
|
{
|
|
|
|
|
assert (i < max_num_aliases);
|
|
|
|
|
preferred[i++] = ent;
|
|
|
|
|
if (debug)
|
|
|
|
|
printf ("found %s for %s.", ent->name, opcode->name);
|
|
|
|
|
}
|
|
|
|
|
++ent;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
|
{
|
|
|
|
|
int m;
|
|
|
|
|
printf ("un-orderd list: ");
|
|
|
|
|
for (m = 0; m < i; ++m)
|
|
|
|
|
printf ("%s, ", preferred[m]->name);
|
|
|
|
|
printf ("\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* There must be at least one alias. */
|
|
|
|
|
assert (i >= 1);
|
|
|
|
|
|
|
|
|
|
/* Sort preferred array according to the priority (from the lowest to the
|
|
|
|
|
highest. */
|
|
|
|
|
if (i > 1)
|
|
|
|
|
{
|
|
|
|
|
int j, k;
|
|
|
|
|
for (j = 0; j < i - 1; ++j)
|
|
|
|
|
{
|
|
|
|
|
for (k = 0; k < i - 1 - j; ++k)
|
|
|
|
|
{
|
|
|
|
|
const aarch64_opcode *t;
|
|
|
|
|
t = preferred [k+1];
|
|
|
|
|
if (opcode_priority (t) < opcode_priority (preferred [k]))
|
|
|
|
|
{
|
|
|
|
|
preferred [k+1] = preferred [k];
|
|
|
|
|
preferred [k] = t;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
|
{
|
|
|
|
|
int m;
|
|
|
|
|
printf ("orderd list: ");
|
|
|
|
|
for (m = 0; m < i; ++m)
|
|
|
|
|
printf ("%s, ", preferred[m]->name);
|
|
|
|
|
printf ("\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Create a link-list of opcode_node with disassemble preference from
|
|
|
|
|
higher to lower. */
|
|
|
|
|
next = &head.next;
|
|
|
|
|
--i;
|
|
|
|
|
while (i >= 0)
|
|
|
|
|
{
|
|
|
|
|
const aarch64_opcode *alias = preferred [i];
|
|
|
|
|
opcode_node *node = new_opcode_node ();
|
|
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
|
printf ("add %s.\n", alias->name);
|
|
|
|
|
|
|
|
|
|
node->index = alias - aarch64_opcode_table;
|
|
|
|
|
*next = node;
|
|
|
|
|
next = &node->next;
|
|
|
|
|
|
|
|
|
|
--i;
|
|
|
|
|
}
|
|
|
|
|
*next = NULL;
|
|
|
|
|
|
|
|
|
|
return head.next;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Create and return alias information.
|
|
|
|
|
Return the address of the created alias info table; return the number
|
|
|
|
|
of table entries in *NUM_PTR. */
|
|
|
|
|
|
|
|
|
|
opcode_node *
|
|
|
|
|
create_alias_info (int *num_ptr)
|
|
|
|
|
{
|
|
|
|
|
int i, num;
|
|
|
|
|
opcode_node *ret;
|
|
|
|
|
const aarch64_opcode *ent;
|
|
|
|
|
|
|
|
|
|
/* Calculate the total number of opcodes that have alias. */
|
|
|
|
|
num = 0;
|
|
|
|
|
ent = aarch64_opcode_table;
|
|
|
|
|
while (ent->name != NULL)
|
|
|
|
|
{
|
|
|
|
|
if (opcode_has_alias (ent))
|
|
|
|
|
{
|
|
|
|
|
/* Assert the alias relationship be flat-structured to keep
|
|
|
|
|
algorithms simple; not allow F_ALIAS and F_HAS_ALIAS both
|
|
|
|
|
specified. */
|
|
|
|
|
assert (!alias_opcode_p (ent));
|
|
|
|
|
++num;
|
|
|
|
|
}
|
|
|
|
|
++ent;
|
|
|
|
|
}
|
|
|
|
|
assert (num_ptr);
|
|
|
|
|
*num_ptr = num;
|
|
|
|
|
|
|
|
|
|
/* The array of real opcodes that have alias(es). */
|
|
|
|
|
ret = malloc (sizeof (opcode_node) * num);
|
|
|
|
|
|
|
|
|
|
/* For each opcode, establish a list of alias nodes in a preferred
|
|
|
|
|
order. */
|
|
|
|
|
for (i = 0, ent = aarch64_opcode_table; i < num; ++i, ++ent)
|
|
|
|
|
{
|
|
|
|
|
opcode_node *node = ret + i;
|
|
|
|
|
while (ent->name != NULL && !opcode_has_alias (ent))
|
|
|
|
|
++ent;
|
|
|
|
|
assert (ent->name != NULL);
|
|
|
|
|
node->index = ent - aarch64_opcode_table;
|
|
|
|
|
node->next = find_alias_opcode (ent);
|
|
|
|
|
assert (node->next);
|
|
|
|
|
}
|
|
|
|
|
assert (i == num);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Release the dynamic memory resource allocated for the generation of the
|
|
|
|
|
alias information. */
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
release_resource_alias_info (opcode_node *alias_info, int num)
|
|
|
|
|
{
|
|
|
|
|
int i = 0;
|
|
|
|
|
opcode_node *node = alias_info;
|
|
|
|
|
|
|
|
|
|
/* Free opcode_node list. */
|
|
|
|
|
for (; i < num; ++i, ++node)
|
|
|
|
|
{
|
|
|
|
|
opcode_node *list = node->next;
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
opcode_node *next = list->next;
|
|
|
|
|
free (list);
|
|
|
|
|
list = next;
|
|
|
|
|
} while (list != NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Free opcode_node array. */
|
|
|
|
|
free (alias_info);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* As a debugging utility, print out the result of the table division, although
|
|
|
|
|
it is not doing much this moment. */
|
|
|
|
|
static void
|
|
|
|
|
print_divide_result (const struct bittree *bittree ATTRIBUTE_UNUSED)
|
|
|
|
|
{
|
|
|
|
|
printf ("max_num_opcodes_at_leaf_node: %d\n", max_num_opcodes_at_leaf_node);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Structure to help generate the operand table. */
|
|
|
|
|
struct operand
|
|
|
|
|
{
|
|
|
|
|
const char *class;
|
|
|
|
|
const char *inserter;
|
|
|
|
|
const char *extractor;
|
|
|
|
|
const char *str;
|
|
|
|
|
const char *flags;
|
|
|
|
|
const char *fields;
|
|
|
|
|
const char *desc;
|
|
|
|
|
unsigned processed : 1;
|
|
|
|
|
unsigned has_inserter : 1;
|
|
|
|
|
unsigned has_extractor : 1;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
typedef struct operand operand;
|
|
|
|
|
|
|
|
|
|
#ifdef X
|
|
|
|
|
#undef X
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef Y
|
|
|
|
|
#undef Y
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef F
|
|
|
|
|
#undef F
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Get the operand information in strings. */
|
|
|
|
|
|
|
|
|
|
static operand operands[] =
|
|
|
|
|
{
|
|
|
|
|
{"NIL", "0", "0", "", "0", "{0}", "<none>", 0, 0, 0},
|
|
|
|
|
#define F(...) #__VA_ARGS__
|
|
|
|
|
#define X(a,b,c,d,e,f,g) \
|
|
|
|
|
{#a, #b, #c, d, #e, "{"f"}", g, 0, 0, 0},
|
|
|
|
|
#define Y(a,b,d,e,f,g) \
|
|
|
|
|
{#a, "ins_"#b, "ext_"#b, d, #e, "{"f"}", g, 0, 0, 0},
|
|
|
|
|
AARCH64_OPERANDS
|
|
|
|
|
{"NIL", "0", "0", "", "0", "{0}", "DUMMY", 0, 0, 0},
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#undef F
|
|
|
|
|
#undef X
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
process_operand_table (void)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
operand *opnd;
|
|
|
|
|
const int num = sizeof (operands) / sizeof (operand);
|
|
|
|
|
|
|
|
|
|
for (i = 0, opnd = operands; i < num; ++i, ++opnd)
|
|
|
|
|
{
|
|
|
|
|
opnd->has_inserter = opnd->inserter[0] != '0';
|
|
|
|
|
opnd->has_extractor = opnd->extractor[0] != '0';
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Generate aarch64_operands in C to the standard output. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_operand_table (void)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
operand *opnd;
|
|
|
|
|
const int num = sizeof (operands) / sizeof (operand);
|
|
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
|
printf ("Enter print_operand_table\n");
|
|
|
|
|
|
|
|
|
|
printf ("\n");
|
|
|
|
|
printf ("const struct aarch64_operand aarch64_operands[] =\n");
|
|
|
|
|
printf ("{\n");
|
|
|
|
|
|
|
|
|
|
for (i = 0, opnd = operands; i < num; ++i, ++opnd)
|
|
|
|
|
{
|
|
|
|
|
char flags[256];
|
|
|
|
|
flags[0] = '\0';
|
|
|
|
|
if (opnd->flags[0] != '0')
|
|
|
|
|
sprintf (flags, "%s", opnd->flags);
|
|
|
|
|
if (opnd->has_inserter)
|
|
|
|
|
{
|
|
|
|
|
if (flags[0] != '\0')
|
|
|
|
|
strcat (flags, " | ");
|
|
|
|
|
strcat (flags, "OPD_F_HAS_INSERTER");
|
|
|
|
|
}
|
|
|
|
|
if (opnd->has_extractor)
|
|
|
|
|
{
|
|
|
|
|
if (flags[0] != '\0')
|
|
|
|
|
strcat (flags, " | ");
|
|
|
|
|
strcat (flags, "OPD_F_HAS_EXTRACTOR");
|
|
|
|
|
}
|
|
|
|
|
if (flags[0] == '\0')
|
|
|
|
|
{
|
|
|
|
|
flags[0] = '0';
|
|
|
|
|
flags[1] = '\0';
|
|
|
|
|
}
|
|
|
|
|
printf (" {AARCH64_OPND_CLASS_%s, \"%s\", %s, %s, \"%s\"},\n",
|
|
|
|
|
opnd->class, opnd->str, flags, opnd->fields, opnd->desc);
|
|
|
|
|
}
|
|
|
|
|
printf ("};\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Generate aarch64_insert_operand in C to the standard output. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_operand_inserter (void)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
operand *opnd;
|
|
|
|
|
const int num = sizeof (operands) / sizeof (operand);
|
|
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
|
printf ("Enter print_operand_inserter\n");
|
|
|
|
|
|
|
|
|
|
printf ("\n");
|
Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 17:11:42 +02:00
|
|
|
|
printf ("bfd_boolean\n");
|
2012-08-13 16:52:54 +02:00
|
|
|
|
printf ("aarch64_insert_operand (const aarch64_operand *self,\n\
|
|
|
|
|
const aarch64_opnd_info *info,\n\
|
Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 17:11:42 +02:00
|
|
|
|
aarch64_insn *code, const aarch64_inst *inst,\n\
|
|
|
|
|
aarch64_operand_error *errors)\n");
|
2012-08-13 16:52:54 +02:00
|
|
|
|
printf ("{\n");
|
|
|
|
|
printf (" /* Use the index as the key. */\n");
|
|
|
|
|
printf (" int key = self - aarch64_operands;\n");
|
|
|
|
|
printf (" switch (key)\n");
|
|
|
|
|
printf (" {\n");
|
|
|
|
|
|
|
|
|
|
for (i = 0, opnd = operands; i < num; ++i, ++opnd)
|
|
|
|
|
opnd->processed = 0;
|
|
|
|
|
|
|
|
|
|
for (i = 0, opnd = operands; i < num; ++i, ++opnd)
|
|
|
|
|
{
|
|
|
|
|
if (!opnd->processed && opnd->has_inserter)
|
|
|
|
|
{
|
|
|
|
|
int j = i + 1;
|
|
|
|
|
const int len = strlen (opnd->inserter);
|
|
|
|
|
operand *opnd2 = opnd + 1;
|
|
|
|
|
printf (" case %u:\n", (unsigned int)(opnd - operands));
|
|
|
|
|
opnd->processed = 1;
|
|
|
|
|
for (; j < num; ++j, ++opnd2)
|
|
|
|
|
{
|
|
|
|
|
if (!opnd2->processed
|
|
|
|
|
&& opnd2->has_inserter
|
|
|
|
|
&& len == strlen (opnd2->inserter)
|
|
|
|
|
&& strncmp (opnd->inserter, opnd2->inserter, len) == 0)
|
|
|
|
|
{
|
|
|
|
|
printf (" case %u:\n", (unsigned int)(opnd2 - operands));
|
|
|
|
|
opnd2->processed = 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 17:11:42 +02:00
|
|
|
|
printf (" return aarch64_%s (self, info, code, inst, errors);\n",
|
2012-08-13 16:52:54 +02:00
|
|
|
|
opnd->inserter);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
printf (" default: assert (0); abort ();\n");
|
|
|
|
|
printf (" }\n");
|
|
|
|
|
printf ("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Generate aarch64_extract_operand in C to the standard output. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_operand_extractor (void)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
operand *opnd;
|
|
|
|
|
const int num = sizeof (operands) / sizeof (operand);
|
|
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
|
printf ("Enter print_operand_extractor\n");
|
|
|
|
|
|
|
|
|
|
printf ("\n");
|
Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 17:11:42 +02:00
|
|
|
|
printf ("bfd_boolean\n");
|
2012-08-13 16:52:54 +02:00
|
|
|
|
printf ("aarch64_extract_operand (const aarch64_operand *self,\n\
|
|
|
|
|
aarch64_opnd_info *info,\n\
|
Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 17:11:42 +02:00
|
|
|
|
aarch64_insn code, const aarch64_inst *inst,\n\
|
|
|
|
|
aarch64_operand_error *errors)\n");
|
2012-08-13 16:52:54 +02:00
|
|
|
|
printf ("{\n");
|
|
|
|
|
printf (" /* Use the index as the key. */\n");
|
|
|
|
|
printf (" int key = self - aarch64_operands;\n");
|
|
|
|
|
printf (" switch (key)\n");
|
|
|
|
|
printf (" {\n");
|
|
|
|
|
|
|
|
|
|
for (i = 0, opnd = operands; i < num; ++i, ++opnd)
|
|
|
|
|
opnd->processed = 0;
|
|
|
|
|
|
|
|
|
|
for (i = 0, opnd = operands; i < num; ++i, ++opnd)
|
|
|
|
|
{
|
|
|
|
|
if (!opnd->processed && opnd->has_extractor)
|
|
|
|
|
{
|
|
|
|
|
int j = i + 1;
|
|
|
|
|
const int len = strlen (opnd->extractor);
|
|
|
|
|
operand *opnd2 = opnd + 1;
|
|
|
|
|
printf (" case %u:\n", (unsigned int)(opnd - operands));
|
|
|
|
|
opnd->processed = 1;
|
|
|
|
|
for (; j < num; ++j, ++opnd2)
|
|
|
|
|
{
|
|
|
|
|
if (!opnd2->processed
|
|
|
|
|
&& opnd2->has_extractor
|
|
|
|
|
&& len == strlen (opnd2->extractor)
|
|
|
|
|
&& strncmp (opnd->extractor, opnd2->extractor, len) == 0)
|
|
|
|
|
{
|
|
|
|
|
printf (" case %u:\n", (unsigned int)(opnd2 - operands));
|
|
|
|
|
opnd2->processed = 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 17:11:42 +02:00
|
|
|
|
printf (" return aarch64_%s (self, info, code, inst, errors);\n",
|
2012-08-13 16:52:54 +02:00
|
|
|
|
opnd->extractor);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
printf (" default: assert (0); abort ();\n");
|
|
|
|
|
printf (" }\n");
|
|
|
|
|
printf ("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Table indexed by opcode enumerator stores the index of the corresponding
|
|
|
|
|
opcode entry in aarch64_opcode_table. */
|
|
|
|
|
static unsigned op_enum_table [OP_TOTAL_NUM];
|
|
|
|
|
|
|
|
|
|
/* Print out the routine which, given the opcode enumerator, returns the
|
|
|
|
|
corresponding opcode entry pointer. */
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_get_opcode (void)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
const int num = OP_TOTAL_NUM;
|
|
|
|
|
const aarch64_opcode *opcode;
|
|
|
|
|
|
|
|
|
|
if (debug)
|
|
|
|
|
printf ("Enter print_get_opcode\n");
|
|
|
|
|
|
|
|
|
|
/* Fill in the internal table. */
|
|
|
|
|
opcode = aarch64_opcode_table;
|
|
|
|
|
while (opcode->name != NULL)
|
|
|
|
|
{
|
|
|
|
|
if (opcode->op != OP_NIL)
|
|
|
|
|
{
|
|
|
|
|
/* Assert opcode enumerator be unique, in other words, no shared by
|
|
|
|
|
different opcodes. */
|
|
|
|
|
if (op_enum_table[opcode->op] != 0)
|
|
|
|
|
{
|
|
|
|
|
fprintf (stderr, "Opcode %u is shared by different %s and %s.\n",
|
|
|
|
|
opcode->op,
|
|
|
|
|
aarch64_opcode_table[op_enum_table[opcode->op]].name,
|
|
|
|
|
opcode->name);
|
|
|
|
|
assert (0);
|
|
|
|
|
abort ();
|
|
|
|
|
}
|
|
|
|
|
assert (opcode->op < OP_TOTAL_NUM);
|
|
|
|
|
op_enum_table[opcode->op] = opcode - aarch64_opcode_table;
|
|
|
|
|
}
|
|
|
|
|
++opcode;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Print the table. */
|
|
|
|
|
printf ("\n");
|
|
|
|
|
printf ("/* Indexed by an enum aarch64_op enumerator, the value is the offset of\n\
|
|
|
|
|
the corresponding aarch64_opcode entry in the aarch64_opcode_table. */\n\n");
|
|
|
|
|
printf ("static const unsigned op_enum_table [] =\n");
|
|
|
|
|
printf ("{\n");
|
|
|
|
|
for (i = 0; i < num; ++i)
|
|
|
|
|
printf (" %u,\n", op_enum_table[i]);
|
|
|
|
|
printf ("};\n");
|
|
|
|
|
|
|
|
|
|
/* Print the function. */
|
|
|
|
|
printf ("\n");
|
|
|
|
|
printf ("/* Given the opcode enumerator OP, return the pointer to the corresponding\n");
|
|
|
|
|
printf (" opcode entry. */\n");
|
|
|
|
|
printf ("\n");
|
|
|
|
|
printf ("const aarch64_opcode *\n");
|
|
|
|
|
printf ("aarch64_get_opcode (enum aarch64_op op)\n");
|
|
|
|
|
printf ("{\n");
|
|
|
|
|
printf (" return aarch64_opcode_table + op_enum_table[op];\n");
|
|
|
|
|
printf ("}\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Print out the content of an opcode table (not in use). */
|
|
|
|
|
static void ATTRIBUTE_UNUSED
|
|
|
|
|
print_table (struct aarch64_opcode* table)
|
|
|
|
|
{
|
|
|
|
|
struct aarch64_opcode *ent = table;
|
|
|
|
|
do
|
|
|
|
|
{
|
|
|
|
|
printf ("%s\t%08x\t%08x\n", ent->name, (unsigned int)ent->opcode,
|
|
|
|
|
(unsigned int)ent->mask);
|
|
|
|
|
} while ((++ent)->name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const char * program_name = NULL;
|
|
|
|
|
|
|
|
|
|
/* Program options. */
|
|
|
|
|
struct option long_options[] =
|
|
|
|
|
{
|
|
|
|
|
{"debug", no_argument, NULL, 'd'},
|
|
|
|
|
{"version", no_argument, NULL, 'V'},
|
|
|
|
|
{"help", no_argument, NULL, 'h'},
|
|
|
|
|
{"gen-opc", no_argument, NULL, 'c'},
|
|
|
|
|
{"gen-asm", no_argument, NULL, 'a'},
|
|
|
|
|
{"gen-dis", no_argument, NULL, 's'},
|
|
|
|
|
{0, no_argument, NULL, 0}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
print_version (void)
|
|
|
|
|
{
|
|
|
|
|
printf ("%s: version 1.0\n", program_name);
|
|
|
|
|
xexit (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
usage (FILE * stream, int status)
|
|
|
|
|
{
|
|
|
|
|
fprintf (stream, "Usage: %s [-V | --version] [-d | --debug] [--help]\n",
|
|
|
|
|
program_name);
|
|
|
|
|
fprintf (stream, "\t[ [-c | --gen-opc] | [-a | --gen-asm] | [-s | --gen-dis] ]\n");
|
|
|
|
|
xexit (status);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
main (int argc, char **argv)
|
|
|
|
|
{
|
|
|
|
|
extern int chdir (char *);
|
|
|
|
|
int c;
|
|
|
|
|
int gen_opcode_p = 0;
|
|
|
|
|
int gen_assembler_p = 0;
|
|
|
|
|
int gen_disassembler_p = 0;
|
|
|
|
|
|
|
|
|
|
program_name = *argv;
|
|
|
|
|
xmalloc_set_program_name (program_name);
|
|
|
|
|
|
|
|
|
|
while ((c = getopt_long (argc, argv, "vVdhacs", long_options, 0)) != EOF)
|
|
|
|
|
switch (c)
|
|
|
|
|
{
|
|
|
|
|
case 'V':
|
|
|
|
|
case 'v':
|
|
|
|
|
print_version ();
|
|
|
|
|
break;
|
|
|
|
|
case 'd':
|
|
|
|
|
debug = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 'h':
|
|
|
|
|
case '?':
|
|
|
|
|
usage (stderr, 0);
|
|
|
|
|
break;
|
|
|
|
|
case 'c':
|
|
|
|
|
gen_opcode_p = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 'a':
|
|
|
|
|
gen_assembler_p = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 's':
|
|
|
|
|
gen_disassembler_p = 1;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
case 0:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (argc == 1 || optind != argc)
|
|
|
|
|
usage (stdout, 1);
|
|
|
|
|
|
|
|
|
|
if (gen_opcode_p + gen_assembler_p + gen_disassembler_p > 1)
|
|
|
|
|
{
|
|
|
|
|
printf ("Please specify only one of the following options\n\
|
|
|
|
|
[-c | --gen-opc] [-a | --gen-asm] [-s | --gen-dis]\n");
|
|
|
|
|
xexit (2);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
struct bittree *decoder_tree;
|
|
|
|
|
|
|
|
|
|
decoder_tree = initialize_decoder_tree ();
|
|
|
|
|
if (debug)
|
|
|
|
|
print_divide_result (decoder_tree);
|
|
|
|
|
|
|
|
|
|
printf ("/* This file is automatically generated by aarch64-gen. Do not edit! */\n");
|
2020-01-01 08:57:01 +01:00
|
|
|
|
printf ("/* Copyright (C) 2012-2020 Free Software Foundation, Inc.\n\
|
2012-08-13 16:52:54 +02:00
|
|
|
|
Contributed by ARM Ltd.\n\
|
|
|
|
|
\n\
|
|
|
|
|
This file is part of the GNU opcodes library.\n\
|
|
|
|
|
\n\
|
|
|
|
|
This library is free software; you can redistribute it and/or modify\n\
|
|
|
|
|
it under the terms of the GNU General Public License as published by\n\
|
|
|
|
|
the Free Software Foundation; either version 3, or (at your option)\n\
|
|
|
|
|
any later version.\n\
|
|
|
|
|
\n\
|
|
|
|
|
It is distributed in the hope that it will be useful, but WITHOUT\n\
|
|
|
|
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n\
|
|
|
|
|
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\n\
|
|
|
|
|
License for more details.\n\
|
|
|
|
|
\n\
|
|
|
|
|
You should have received a copy of the GNU General Public License\n\
|
|
|
|
|
along with this program; see the file COPYING3. If not,\n\
|
|
|
|
|
see <http://www.gnu.org/licenses/>. */\n");
|
|
|
|
|
|
|
|
|
|
printf ("\n");
|
|
|
|
|
printf ("#include \"sysdep.h\"\n");
|
|
|
|
|
if (gen_opcode_p)
|
|
|
|
|
printf ("#include \"aarch64-opc.h\"\n");
|
|
|
|
|
if (gen_assembler_p)
|
|
|
|
|
printf ("#include \"aarch64-asm.h\"\n");
|
|
|
|
|
if (gen_disassembler_p)
|
|
|
|
|
printf ("#include \"aarch64-dis.h\"\n");
|
|
|
|
|
printf ("\n");
|
|
|
|
|
|
|
|
|
|
/* Generate opcode entry lookup for the disassembler. */
|
|
|
|
|
if (gen_disassembler_p)
|
|
|
|
|
{
|
|
|
|
|
print_decision_tree (decoder_tree);
|
|
|
|
|
print_find_next_opcode (decoder_tree);
|
|
|
|
|
release_resource_decoder_tree (decoder_tree);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Generate alias opcode handling for the assembler or the disassembler. */
|
|
|
|
|
if (gen_assembler_p || gen_disassembler_p)
|
|
|
|
|
{
|
|
|
|
|
int num;
|
|
|
|
|
opcode_node *alias_info = create_alias_info (&num);
|
|
|
|
|
|
|
|
|
|
if (gen_assembler_p)
|
|
|
|
|
print_find_real_opcode (alias_info, num);
|
|
|
|
|
|
|
|
|
|
if (gen_disassembler_p)
|
|
|
|
|
{
|
|
|
|
|
print_find_alias_opcode (alias_info, num);
|
|
|
|
|
print_find_next_alias_opcode (alias_info, num);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
release_resource_alias_info (alias_info, num);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Generate operand table. */
|
|
|
|
|
process_operand_table ();
|
|
|
|
|
|
|
|
|
|
if (gen_assembler_p)
|
|
|
|
|
print_operand_inserter ();
|
|
|
|
|
|
|
|
|
|
if (gen_disassembler_p)
|
|
|
|
|
print_operand_extractor ();
|
|
|
|
|
|
|
|
|
|
if (gen_opcode_p)
|
|
|
|
|
print_operand_table ();
|
|
|
|
|
|
|
|
|
|
/* Generate utility to return aarch64_opcode entry given an enumerator. */
|
|
|
|
|
if (gen_opcode_p)
|
|
|
|
|
print_get_opcode ();
|
|
|
|
|
|
|
|
|
|
exit (0);
|
|
|
|
|
}
|