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2002-03-02 Chris Demetriou <cgd@broadcom.com> 

* interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
	* mips.igen (LL, CxC1, MxC1): Likewise.
This commit is contained in:
Chris Demetriou 2002-03-03 06:49:43 +00:00
parent c1e8ada406
commit 043b7057fd
3 changed files with 13 additions and 8 deletions
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5
sim/mips/ChangeLog
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@ -1,3 +1,8 @@
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
* mips.igen (LL, CxC1, MxC1): Likewise.
2002-03-02 Chris Demetriou <cgd@broadcom.com> 2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt, * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,

2
sim/mips/interp.c
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@ -1426,7 +1426,7 @@ load_word (SIM_DESC sd,
LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
isDATA, isREAL); isDATA, isREAL);
byte = (vaddr & mask) ^ (bigend << 2); byte = (vaddr & mask) ^ (bigend << 2);
return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32); return EXTEND32 (memval >> (8 * byte));
} }
} }

14
sim/mips/mips.igen
View File

@ -1716,7 +1716,7 @@
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
byte = ((vaddr & mask) ^ (bigend << shift)); byte = ((vaddr & mask) ^ (bigend << shift));
GPR[RT] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32)); GPR[RT] = EXTEND32 (memval >> (8 * byte));
LLBIT = 1; LLBIT = 1;
} }
} }
@ -3269,9 +3269,9 @@
else else
{ /* control from */ { /* control from */
if (FS == 0) if (FS == 0)
PENDING_FILL(RT,SIGNEXTEND(FCR0,32)); PENDING_FILL(RT, EXTEND32 (FCR0));
else if (FS == 31) else if (FS == 31)
PENDING_FILL(RT,SIGNEXTEND(FCR31,32)); PENDING_FILL(RT, EXTEND32 (FCR31));
/* else NOP */ /* else NOP */
} }
} }
@ -3310,12 +3310,12 @@
if (FS == 0) if (FS == 0)
{ {
TRACE_ALU_INPUT1 (FCR0); TRACE_ALU_INPUT1 (FCR0);
GPR[RT] = SIGNEXTEND (FCR0, 32); GPR[RT] = EXTEND32 (FCR0);
} }
else if (FS == 31) else if (FS == 31)
{ {
TRACE_ALU_INPUT1 (FCR31); TRACE_ALU_INPUT1 (FCR31);
GPR[RT] = SIGNEXTEND (FCR31, 32); GPR[RT] = EXTEND32 (FCR31);
} }
TRACE_ALU_RESULT (GPR[RT]); TRACE_ALU_RESULT (GPR[RT]);
/* else NOP */ /* else NOP */
@ -3656,7 +3656,7 @@
PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT])); PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
} }
else /*MFC1*/ else /*MFC1*/
PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32)); PENDING_FILL (RT, EXTEND32 (FGR[FS]));
} }
010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
"m%s<X>c1 r<RT>, f<FS>" "m%s<X>c1 r<RT>, f<FS>"
@ -3672,7 +3672,7 @@
/*MTC1*/ /*MTC1*/
StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT])); StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
else /*MFC1*/ else /*MFC1*/
GPR[RT] = SIGNEXTEND(FGR[FS],32); GPR[RT] = EXTEND32 (FGR[FS]);
} }