[PATCH 41/57][Arm][OBJDUMP] Add support for MVE instructions: vld[24] and vst[24]
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new reasons. (is_mve_encoding_conflict): Handle new instructions. (is_mve_unpredictable): Likewise. (mve_opcodes): Add new instructions. (print_mve_unpredictable): Handle new reasons. (print_mve_register_blocks): New print function. (print_mve_size): Handle new instructions. (print_insn_mve): Likewise.
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Andre Vieira
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9743db035e
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04d54ace12
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@ -1,3 +1,16 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (enum mve_instructions): Add new instructions.
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(enum mve_unpredictable): Add new reasons.
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(is_mve_encoding_conflict): Handle new instructions.
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(is_mve_unpredictable): Likewise.
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(mve_opcodes): Add new instructions.
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(print_mve_unpredictable): Handle new reasons.
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(print_mve_register_blocks): New print function.
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(print_mve_size): Handle new instructions.
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(print_insn_mve): Likewise.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -98,6 +98,10 @@ enum mve_instructions
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MVE_VHSUB_T1,
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MVE_VHSUB_T2,
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MVE_VRHADD,
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MVE_VLD2,
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MVE_VLD4,
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MVE_VST2,
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MVE_VST4,
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MVE_NONE
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};
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@ -110,6 +114,12 @@ enum mve_unpredictable
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UNPRED_R13, /* Unpredictable because r13 (sp) or
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r15 (sp) used. */
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UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
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UNPRED_Q_GT_4, /* Unpredictable because
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vec reg start > 4 (vld4/st4). */
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UNPRED_Q_GT_6, /* Unpredictable because
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vec reg start > 6 (vld2/st2). */
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UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
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and WB bit = 1. */
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UNPRED_NONE /* No unpredictable behavior. */
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};
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@ -1823,7 +1833,11 @@ static const struct opcode32 neon_opcodes[] =
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%n print vector comparison code for predicated instruction
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%v print vector predicate for instruction in predicated
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block
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%w print writeback mode for MVE v{st,ld}[24]
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%B print v{st,ld}[24] any one operands
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%<bitfield>r print as an ARM register
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%<bitfield>d print the bitfield in decimal
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%<bitfield>Q print as a MVE Q register
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%<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
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UNPREDICTABLE
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@ -1997,6 +2011,42 @@ static const struct mopcode32 mve_opcodes[] =
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0xef000140, 0xef811f51,
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"vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VLD2. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLD2,
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0xfc901e00, 0xff901e5f,
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"vld2%5d.%7-8s\t%B, [%16-19r]%w"},
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/* Vector VLD4. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLD4,
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0xfc901e01, 0xff901e1f,
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"vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
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/* Vector VST2 no writeback. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VST2,
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0xfc801e00, 0xffb01e5f,
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"vst2%5d.%7-8s\t%B, [%16-19r]"},
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/* Vector VST2 writeback. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VST2,
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0xfca01e00, 0xffb01e5f,
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"vst2%5d.%7-8s\t%B, [%16-19r]!"},
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/* Vector VST4 no writeback. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VST4,
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0xfc801e01, 0xffb01e1f,
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"vst4%5-6d.%7-8s\t%B, [%16-19r]"},
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/* Vector VST4 writeback. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VST4,
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0xfca01e01, 0xffb01e1f,
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"vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
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{ARM_FEATURE_CORE_LOW (0),
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MVE_NONE,
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0x00000000, 0x00000000, 0}
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@ -4015,6 +4065,15 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VLD2:
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case MVE_VLD4:
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case MVE_VST2:
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case MVE_VST4:
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if (arm_decode_field (given, 7, 8) == 3)
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return TRUE;
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else
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return FALSE;
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default:
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return FALSE;
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@ -4132,6 +4191,58 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VLD2:
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case MVE_VST2:
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{
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unsigned long rn = arm_decode_field (given, 16, 19);
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if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
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{
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*unpredictable_code = UNPRED_R13_AND_WB;
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return TRUE;
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}
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if (rn == 0xf)
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{
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*unpredictable_code = UNPRED_R15;
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return TRUE;
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}
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if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
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{
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*unpredictable_code = UNPRED_Q_GT_6;
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return TRUE;
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}
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else
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return FALSE;
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}
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case MVE_VLD4:
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case MVE_VST4:
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{
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unsigned long rn = arm_decode_field (given, 16, 19);
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if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
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{
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*unpredictable_code = UNPRED_R13_AND_WB;
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return TRUE;
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}
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if (rn == 0xf)
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{
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*unpredictable_code = UNPRED_R15;
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return TRUE;
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}
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if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
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{
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*unpredictable_code = UNPRED_Q_GT_4;
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return TRUE;
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}
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else
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return FALSE;
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}
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default:
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return FALSE;
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}
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@ -4185,11 +4296,61 @@ print_mve_unpredictable (struct disassemble_info *info,
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func (stream, "use of r15 (pc)");
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break;
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case UNPRED_Q_GT_4:
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func (stream, "start register block > r4");
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break;
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case UNPRED_Q_GT_6:
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func (stream, "start register block > r6");
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break;
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case UNPRED_R13_AND_WB:
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func (stream, "use of r13 and write back");
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break;
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case UNPRED_NONE:
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break;
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}
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}
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/* Print register block operand for mve vld2/vld4/vst2/vld4. */
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static void
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print_mve_register_blocks (struct disassemble_info *info,
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unsigned long given,
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enum mve_instructions matched_insn)
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{
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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unsigned long q_reg_start = arm_decode_field_multiple (given,
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13, 15,
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22, 22);
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switch (matched_insn)
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{
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case MVE_VLD2:
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case MVE_VST2:
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if (q_reg_start <= 6)
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func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
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else
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func (stream, "<illegal reg q%ld>", q_reg_start);
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break;
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case MVE_VLD4:
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case MVE_VST4:
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if (q_reg_start <= 4)
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func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
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q_reg_start + 1, q_reg_start + 2,
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q_reg_start + 3);
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else
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func (stream, "<illegal reg q%ld>", q_reg_start);
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break;
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default:
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break;
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}
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}
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static void
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print_instruction_predicate (struct disassemble_info *info)
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{
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@ -4222,6 +4383,8 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VHADD_T2:
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case MVE_VHSUB_T1:
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case MVE_VHSUB_T2:
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case MVE_VLD2:
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case MVE_VLD4:
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case MVE_VPT_VEC_T1:
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case MVE_VPT_VEC_T2:
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case MVE_VPT_VEC_T3:
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@ -4229,6 +4392,8 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VPT_VEC_T5:
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case MVE_VPT_VEC_T6:
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case MVE_VRHADD:
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case MVE_VST2:
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case MVE_VST4:
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if (size <= 3)
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func (stream, "%s", mve_vec_sizename[size]);
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else
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@ -5721,6 +5886,15 @@ print_insn_mve (struct disassemble_info *info, long given)
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print_instruction_predicate (info);
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break;
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case 'w':
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if (arm_decode_field (given, 21, 21) == 1)
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func (stream, "!");
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break;
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case 'B':
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print_mve_register_blocks (info, given, insn->mve_op);
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break;
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case '0': case '1': case '2': case '3': case '4':
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case '5': case '6': case '7': case '8': case '9':
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{
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@ -5747,6 +5921,10 @@ print_insn_mve (struct disassemble_info *info, long given)
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case 'r':
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func (stream, "%s", arm_regnames[value]);
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break;
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case 'd':
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func (stream, "%ld", value);
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value_in_comment = value;
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break;
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case 'Q':
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if (value & 0x8)
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func (stream, "<illegal reg q%ld.5>", value);
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