* mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):
Add tx49 insns and configury.
This commit is contained in:
Gavin Romig-Koch
parent
6205f37913
commit
0cca41d47a
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@ -249,6 +249,34 @@ else
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done
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fi
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tx49_files="ChangeLog mips-opc.c"
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if ( echo $* | grep keep\-tx49 > /dev/null ) ; then
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for i in $tx49_files ; do
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if test ! -d $i && (grep sanitize-tx49 $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Keeping tx49 stuff in $i
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fi
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fi
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done
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else
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for i in $tx49_files ; do
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if test ! -d $i && (grep sanitize-tx49 $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Removing traces of \"tx49\" from $i...
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fi
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cp $i new
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sed '/start\-sanitize\-tx49/,/end-\sanitize\-tx49/d' < $i > new
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if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
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if [ -n "${verbose}" ] ; then
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echo Caching $i in .Recover...
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fi
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mv $i .Recover
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fi
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mv new $i
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fi
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done
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fi
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tic80_files="ChangeLog Makefile.in Makefile.am configure.in configure disassemble.c"
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if ( echo $* | grep keep\-tic80 > /dev/null ) ; then
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for i in $tic80_files ; do
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@ -1,3 +1,10 @@
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start-sanitize-tx49
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Wed Oct 29 15:10:56 1997 Gavin Koch <gavin@cygnus.com>
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* mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):
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Add tx49 insns and configury.
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end-sanitize-tx49
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Tue Oct 28 17:59:32 1997 Ken Raeburn <raeburn@cygnus.com>
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* mips-opc.c (ffc, ffs): Fix mask.
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@ -76,6 +76,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define L1 INSN_4010
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#define V1 INSN_4100
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#define T3 INSN_3900
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/* start-sanitize-tx49 */
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#define T4 INSN_4900
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/* end-sanitize-tx49 */
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/* start-sanitize-vr5400 */
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#define N5 INSN_5400
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/* end-sanitize-vr5400 */
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@ -84,11 +87,20 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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/* end-sanitize-r5900 */
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#define G1 (T3 \
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/* start-sanitize-tx49 */ \
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| T4 \
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/* end-sanitize-tx49 */ \
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/* start-sanitize-r5900 */ \
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| T5 \
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/* end-sanitize-r5900 */ \
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)
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#define G2 (T3 \
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/* start-sanitize-tx49 */ \
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| T4 \
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/* end-sanitize-tx49 */ \
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)
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/* The order of overloaded instructions matters. Label arguments and
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register arguments look the same. Instructions that can have either
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@ -312,7 +324,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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/* dctr and dctw are used on the r5000. */
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{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
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{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
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{"deret", "", 0x4200001f, 0xffffffff, 0, T3 },
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{"deret", "", 0x4200001f, 0xffffffff, 0, G2 },
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/* For ddiv, see the comments about div. */
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{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
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{"ddiv", "d,v,t", 3, (int) M_DDIV_3, INSN_MACRO },
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@ -357,8 +369,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"dmulo", "d,v,I", 3, (int) M_DMULO_I, INSN_MACRO },
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{"dmulou", "d,v,t", 3, (int) M_DMULOU, INSN_MACRO },
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{"dmulou", "d,v,I", 3, (int) M_DMULOU_I, INSN_MACRO },
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{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
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{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
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{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3},
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{"dmult", "d,s,t", 0x0000001c, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T4},
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{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3},
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{"dmultu", "d,s,t", 0x0000001d, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T4},
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{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */
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{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/
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{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
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@ -505,20 +519,16 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, T5 },
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/* end-sanitize-r5900 */
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{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
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{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T3 },
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{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T3 },
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{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, G1 },
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{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1 },
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/* start-sanitize-r5900 */
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{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
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{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
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{"madd1", "s,t", 0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
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{"madd1", "d,s,t", 0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
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/* end-sanitize-r5900 */
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{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
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{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T3 },
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{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T3 },
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{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, G1 },
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{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, G1 },
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/* start-sanitize-r5900 */
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{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
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{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
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{"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, T5 },
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{"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T5 },
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/* end-sanitize-r5900 */
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@ -772,7 +782,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"pxor", "d,v,t", 0x700004c9, 0xfc0007ff, WR_d|RD_s|RD_t, T5 },
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/* end-sanitize-r5900 */
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{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4 },
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{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|T4 },
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{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
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/* start-sanitize-r5900 */
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@ -816,8 +826,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 },
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{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO },
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{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO },
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{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, T3 },
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{"sdbbp", "c", 0x0000000e, 0xfc00003f, TRAP, T3 },
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{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2 },
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{"sdbbp", "c", 0x0000000e, 0xfc00003f, TRAP, G2 },
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{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
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{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
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{"sdc1", "T,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
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