[PATCH 46/57][Arm][OBJDUMP] Add support for MVE instructions: vmovl, vmull, vqdmull, vqmovn, vqmovun and vmovn
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
This commit is contained in:
Andre Vieira
parent
c507f10b07
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14925797f8
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@ -1,3 +1,13 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (enum mve_instructions): Add new instructions.
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(is_mve_encoding_conflict): Handle new instructions.
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(is_mve_undefined): Likewise.
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(is_mve_unpredictable): Likewise.
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(print_mve_size): Likewise.
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(print_insn_mve): Likewise.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -144,6 +144,14 @@ enum mve_instructions
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MVE_VBIC_IMM,
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MVE_VBIC_REG,
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MVE_VMOVX,
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MVE_VMOVL,
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MVE_VMOVN,
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MVE_VMULL_INT,
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MVE_VMULL_POLY,
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MVE_VQDMULL_T1,
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MVE_VQDMULL_T2,
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MVE_VQMOVN,
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MVE_VQMOVUN,
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MVE_NONE
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};
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@ -1913,6 +1921,7 @@ static const struct opcode32 neon_opcodes[] =
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%B print v{st,ld}[24] any one operands
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%E print vmov, vmvn, vorr, vbic encoded constant
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%N print generic index for vmov
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%T print bottom ('b') or top ('t') of source register
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%<bitfield>r print as an ARM register
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%<bitfield>d print the bitfield in decimal
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@ -2280,12 +2289,36 @@ static const struct mopcode32 mve_opcodes[] =
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0xee100b10, 0xff100f1f,
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"vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
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/* Vector VMOVL long. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMOVL,
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0xeea00f40, 0xefa70fd1,
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"vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VMOV and narrow. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMOVN,
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0xfe310e81, 0xffb30fd1,
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"vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Floating point move extract. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VMOVX,
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0xfeb00a40, 0xffbf0fd0,
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"vmovx.f16\t%22,12-15F, %5,0-3F"},
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/* Vector VMULL integer. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMULL_INT,
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0xee010e00, 0xef810f51,
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"vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VMULL polynomial. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMULL_POLY,
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0xee310e00, 0xefb10f51,
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"vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VMVN immediate to vector. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMVN_IMM,
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@ -2310,6 +2343,30 @@ static const struct mopcode32 mve_opcodes[] =
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0xef200150, 0xffb11f51,
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"vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQDMULL T1 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQDMULL_T1,
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0xee300f01, 0xefb10f51,
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"vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VQDMULL T2 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQDMULL_T2,
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0xee300f60, 0xefb10f70,
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"vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VQMOVN. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQMOVN,
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0xee330e01, 0xefb30fd1,
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"vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VQMOVUN. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VQMOVUN,
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0xee310e81, 0xffb30fd1,
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"vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VRINT floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VRINT_FP,
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@ -4420,6 +4477,7 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VMULL_INT:
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case MVE_VHADD_T2:
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case MVE_VHSUB_T2:
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case MVE_VCMP_VEC_T1:
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@ -4502,6 +4560,23 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VMOVL:
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{
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unsigned long size = arm_decode_field (given, 19, 20);
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if ((size == 0) || (size == 3))
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return TRUE;
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else
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return FALSE;
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}
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case MVE_VMOVN:
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case MVE_VQMOVUN:
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case MVE_VQMOVN:
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if (arm_decode_field (given, 18, 19) == 3)
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return TRUE;
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else
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return FALSE;
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default:
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return FALSE;
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@ -4855,6 +4930,15 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VMOVN:
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if (arm_decode_field (given, 18, 19) == 2)
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{
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*undefined_code = UNDEF_SIZE_2;
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return TRUE;
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}
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else
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return FALSE;
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default:
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return FALSE;
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}
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@ -5126,6 +5210,86 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VMULL_INT:
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{
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unsigned long Qd;
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unsigned long Qm;
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unsigned long Qn;
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if (arm_decode_field (given, 20, 21) == 2)
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{
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Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
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Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
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Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
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if ((Qd == Qn) || (Qd == Qm))
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{
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*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
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return TRUE;
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}
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else
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return FALSE;
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}
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else
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return FALSE;
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}
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case MVE_VQDMULL_T1:
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{
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unsigned long Qd;
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unsigned long Qm;
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unsigned long Qn;
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if (arm_decode_field (given, 28, 28) == 1)
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{
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Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
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Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
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Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
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if ((Qd == Qn) || (Qd == Qm))
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{
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*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
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return TRUE;
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}
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else
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return FALSE;
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}
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else
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return FALSE;
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}
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case MVE_VQDMULL_T2:
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{
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unsigned long gpr = arm_decode_field (given, 0, 3);
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if (gpr == 0xd)
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{
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*unpredictable_code = UNPRED_R13;
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return TRUE;
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}
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else if (gpr == 0xf)
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{
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*unpredictable_code = UNPRED_R15;
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return TRUE;
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}
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if (arm_decode_field (given, 28, 28) == 1)
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{
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unsigned long Qd
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= arm_decode_field_multiple (given, 13, 15, 22, 22);
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unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
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if ((Qd == Qn))
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{
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*unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
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return TRUE;
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}
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else
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return FALSE;
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}
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return FALSE;
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}
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default:
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return FALSE;
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}
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@ -5804,6 +5968,24 @@ print_mve_size (struct disassemble_info *info,
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func (stream, "16");
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break;
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case MVE_VMOVN:
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case MVE_VQDMULL_T1:
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case MVE_VQDMULL_T2:
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case MVE_VQMOVN:
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case MVE_VQMOVUN:
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if (size == 0)
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func (stream, "16");
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else if (size == 1)
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func (stream, "32");
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break;
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case MVE_VMOVL:
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if (size == 1)
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func (stream, "8");
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else if (size == 2)
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func (stream, "16");
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break;
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case MVE_VDUP:
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switch (size)
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{
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@ -5868,6 +6050,13 @@ print_mve_size (struct disassemble_info *info,
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}
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break;
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case MVE_VMULL_POLY:
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if (size == 0)
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func (stream, "p8");
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else if (size == 1)
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func (stream, "p16");
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break;
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case MVE_VMVN_IMM:
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switch (size)
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{
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@ -7443,6 +7632,13 @@ print_insn_mve (struct disassemble_info *info, long given)
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print_mve_vmov_index (info, given);
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break;
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case 'T':
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if (arm_decode_field (given, 12, 12) == 0)
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func (stream, "b");
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else
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func (stream, "t");
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break;
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case '0': case '1': case '2': case '3': case '4':
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case '5': case '6': case '7': case '8': case '9':
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{
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