[PATCH 45/57][Arm][OBJDUMP] Add support for MVE instructions: vmov, vmvn, vorr, vorn, vmovx and vbic
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new reasons. (enum mve_undefined): Likewise. (is_mve_okay_in_it): Handle new isntructions. (is_mve_encoding_conflict): Likewise. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_vmov_index): Likewise. (print_simd_imm8): Likewise. (print_mve_undefined): Likewise. (print_mve_unpredictable): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
This commit is contained in:
Andre Vieira
parent
bf0b396de7
commit
c507f10b07
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@ -1,3 +1,20 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (enum mve_instructions): Add new instructions.
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(enum mve_unpredictable): Add new reasons.
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(enum mve_undefined): Likewise.
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(is_mve_okay_in_it): Handle new isntructions.
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(is_mve_encoding_conflict): Likewise.
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(is_mve_undefined): Likewise.
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(is_mve_unpredictable): Likewise.
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(print_mve_vmov_index): Likewise.
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(print_simd_imm8): Likewise.
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(print_mve_undefined): Likewise.
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(print_mve_unpredictable): Likewise.
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(print_mve_size): Likewise.
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(print_insn_mve): Likewise.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -129,6 +129,21 @@ enum mve_instructions
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MVE_VCVT_FP_HALF_FP,
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MVE_VCVT_FROM_FP_TO_INT,
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MVE_VRINT_FP,
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MVE_VMOV_HFP_TO_GP,
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MVE_VMOV_GP_TO_VEC_LANE,
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MVE_VMOV_IMM_TO_VEC,
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MVE_VMOV_VEC_TO_VEC,
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MVE_VMOV2_VEC_LANE_TO_GP,
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MVE_VMOV2_GP_TO_VEC_LANE,
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MVE_VMOV_VEC_LANE_TO_GP,
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MVE_VMVN_IMM,
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MVE_VMVN_REG,
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MVE_VORR_IMM,
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MVE_VORR_REG,
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MVE_VORN,
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MVE_VBIC_IMM,
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MVE_VBIC_REG,
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MVE_VMOVX,
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MVE_NONE
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};
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@ -152,12 +167,17 @@ enum mve_unpredictable
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UNPRED_OS, /* Unpredictable because offset scaled == 1. */
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UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
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same. */
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UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
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size = 1. */
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UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
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size = 2. */
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UNPRED_NONE /* No unpredictable behavior. */
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};
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enum mve_undefined
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{
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UNDEF_SIZE_0, /* undefined because size == 0. */
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UNDEF_SIZE_2, /* undefined because size == 2. */
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UNDEF_SIZE_3, /* undefined because size == 3. */
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UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
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UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
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@ -169,6 +189,12 @@ enum mve_undefined
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UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
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UNDEF_VCVT_IMM6, /* imm6 < 32. */
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UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
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UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
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op1 == (0 or 1). */
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UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
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op2 == 0 and op1 == (0 or 1). */
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UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
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in {0xx1, x0x1}. */
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UNDEF_NONE /* no undefined behavior. */
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};
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@ -1885,15 +1911,19 @@ static const struct opcode32 neon_opcodes[] =
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%o print offset scaled for vldr[hwd] and vstr[hwd]
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%w print writeback mode for MVE v{st,ld}[24]
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%B print v{st,ld}[24] any one operands
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%E print vmov, vmvn, vorr, vbic encoded constant
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%N print generic index for vmov
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%<bitfield>r print as an ARM register
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%<bitfield>d print the bitfield in decimal
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%<bitfield>Q print as a MVE Q register
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%<bitfield>F print as a MVE S register
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%<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
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UNPREDICTABLE
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%<bitfield>s print size for vector predicate & non VMOV instructions
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%<bitfield>i print immediate for vstr/vldr reg +/- imm
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%<bitfield>k print immediate for vector conversion instruction
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%<bitfield>x print the bitfield in hex.
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*/
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static const struct mopcode32 mve_opcodes[] =
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@ -1948,6 +1978,18 @@ static const struct mopcode32 mve_opcodes[] =
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0xfe011f40, 0xff811f50,
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"vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
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/* Vector VBIC immediate. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VBIC_IMM,
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0xef800070, 0xefb81070,
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"vbic%v.i%8-11s\t%13-15,22Q, %E"},
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/* Vector VBIC register. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VBIC_REG,
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0xef100150, 0xffb11f51,
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"vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VCMP floating point T1. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCMP_FP_T1,
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@ -2171,6 +2213,103 @@ static const struct mopcode32 mve_opcodes[] =
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0xec101f00, 0xfe101f80,
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"vldrw%v.u32\t%13-15,22Q, %d"},
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/* Vector VMOV between gpr and half precision register, op == 0. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VMOV_HFP_TO_GP,
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0xee000910, 0xfff00f7f,
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"vmov.f16\t%7,16-19F, %12-15r"},
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/* Vector VMOV between gpr and half precision register, op == 1. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VMOV_HFP_TO_GP,
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0xee100910, 0xfff00f7f,
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"vmov.f16\t%12-15r, %7,16-19F"},
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VMOV_GP_TO_VEC_LANE,
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0xee000b10, 0xff900f1f,
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"vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
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/* Vector VORR immediate to vector.
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NOTE: MVE_VORR_IMM must appear in the table
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before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VORR_IMM,
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0xef800050, 0xefb810f0,
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"vorr%v.i%8-11s\t%13-15,22Q, %E"},
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/* Vector VMOV immediate to vector,
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cmode == 11x1 -> VMVN which is UNDEFINED
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for such a cmode. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
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/* Vector VMOV immediate to vector. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMOV_IMM_TO_VEC,
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0xef800050, 0xefb810d0,
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"vmov%v.%5,8-11s\t%13-15,22Q, %E"},
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/* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMOV2_VEC_LANE_TO_GP,
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0xec000f00, 0xffb01ff0,
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"vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
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/* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMOV2_VEC_LANE_TO_GP,
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0xec000f10, 0xffb01ff0,
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"vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
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/* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMOV2_GP_TO_VEC_LANE,
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0xec100f00, 0xffb01ff0,
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"vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
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/* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMOV2_GP_TO_VEC_LANE,
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0xec100f10, 0xffb01ff0,
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"vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
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/* Vector VMOV Vector lane to gpr. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VMOV_VEC_LANE_TO_GP,
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0xee100b10, 0xff100f1f,
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"vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
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/* Floating point move extract. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VMOVX,
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0xfeb00a40, 0xffbf0fd0,
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"vmovx.f16\t%22,12-15F, %5,0-3F"},
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/* Vector VMVN immediate to vector. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMVN_IMM,
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0xef800070, 0xefb810f0,
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"vmvn%v.i%8-11s\t%13-15,22Q, %E"},
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/* Vector VMVN register. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VMVN_REG,
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0xffb005c0, 0xffbf1fd1,
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"vmvn%v\t%13-15,22Q, %1-3,5Q"},
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/* Vector VORN, vector bitwise or not. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VORN,
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0xef300150, 0xffb11f51,
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"vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VORR register. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VORR_REG,
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0xef200150, 0xffb11f51,
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"vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VRINT floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VRINT_FP,
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@ -4127,7 +4266,16 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream,
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static bfd_boolean
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is_mve_okay_in_it (enum mve_instructions matched_insn)
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{
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return FALSE;
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switch (matched_insn)
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{
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case MVE_VMOV_GP_TO_VEC_LANE:
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case MVE_VMOV2_VEC_LANE_TO_GP:
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case MVE_VMOV2_GP_TO_VEC_LANE:
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case MVE_VMOV_VEC_LANE_TO_GP:
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return TRUE;
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default:
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return FALSE;
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}
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}
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static bfd_boolean
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@ -4320,6 +4468,40 @@ is_mve_encoding_conflict (unsigned long given,
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case MVE_VCVT_FP_FIX_VEC:
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return (arm_decode_field (given, 16, 21) & 0x38) == 0;
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case MVE_VBIC_IMM:
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case MVE_VORR_IMM:
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{
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unsigned long cmode = arm_decode_field (given, 8, 11);
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if ((cmode & 1) == 0)
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return TRUE;
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else if ((cmode & 0xc) == 0xc)
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return TRUE;
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else
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return FALSE;
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}
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case MVE_VMVN_IMM:
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{
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unsigned long cmode = arm_decode_field (given, 8, 11);
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if ((cmode & 9) == 1)
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return TRUE;
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else if ((cmode & 5) == 1)
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return TRUE;
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else if ((cmode & 0xe) == 0xe)
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return TRUE;
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else
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return FALSE;
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}
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case MVE_VMOV_IMM_TO_VEC:
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if ((arm_decode_field (given, 5, 5) == 1)
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&& (arm_decode_field (given, 8, 11) != 0xe))
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return TRUE;
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else
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return FALSE;
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default:
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return FALSE;
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@ -4612,6 +4794,67 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VMOV_VEC_LANE_TO_GP:
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{
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unsigned long op1 = arm_decode_field (given, 21, 22);
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unsigned long op2 = arm_decode_field (given, 5, 6);
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unsigned long u = arm_decode_field (given, 23, 23);
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if ((op2 == 0) && (u == 1))
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{
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if ((op1 == 0) || (op1 == 1))
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{
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*undefined_code = UNDEF_BAD_U_OP1_OP2;
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return TRUE;
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}
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else
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return FALSE;
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}
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else if (op2 == 2)
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{
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if ((op1 == 0) || (op1 == 1))
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{
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*undefined_code = UNDEF_BAD_OP1_OP2;
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return TRUE;
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}
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else
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return FALSE;
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}
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return FALSE;
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}
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case MVE_VMOV_GP_TO_VEC_LANE:
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if (arm_decode_field (given, 5, 6) == 2)
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{
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unsigned long op1 = arm_decode_field (given, 21, 22);
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if ((op1 == 0) || (op1 == 1))
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{
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*undefined_code = UNDEF_BAD_OP1_OP2;
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return TRUE;
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}
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else
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return FALSE;
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}
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else
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return FALSE;
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case MVE_VMOV_IMM_TO_VEC:
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if (arm_decode_field (given, 5, 5) == 0)
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{
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unsigned long cmode = arm_decode_field (given, 8, 11);
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if (((cmode & 9) == 1) || ((cmode & 5) == 1))
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{
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*undefined_code = UNDEF_OP_0_BAD_CMODE;
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return TRUE;
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}
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else
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return FALSE;
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}
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else
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return FALSE;
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default:
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return FALSE;
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}
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@ -4837,6 +5080,8 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VMOV2_VEC_LANE_TO_GP:
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case MVE_VMOV2_GP_TO_VEC_LANE:
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case MVE_VCVT_BETWEEN_FP_INT:
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case MVE_VCVT_FROM_FP_TO_INT:
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{
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@ -4862,11 +5107,224 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VMOV_HFP_TO_GP:
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case MVE_VMOV_GP_TO_VEC_LANE:
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case MVE_VMOV_VEC_LANE_TO_GP:
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{
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unsigned long rda = arm_decode_field (given, 12, 15);
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if (rda == 0xd)
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{
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*unpredictable_code = UNPRED_R13;
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return TRUE;
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}
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else if (rda == 0xf)
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{
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*unpredictable_code = UNPRED_R15;
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return TRUE;
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}
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return FALSE;
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}
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default:
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return FALSE;
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}
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}
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static void
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print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
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{
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unsigned long op1 = arm_decode_field (given, 21, 22);
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unsigned long op2 = arm_decode_field (given, 5, 6);
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unsigned long h = arm_decode_field (given, 16, 16);
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unsigned long index, esize, targetBeat, idx;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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if ((op1 & 0x2) == 0x2)
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{
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index = op2;
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esize = 8;
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}
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else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
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{
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index = op2 >> 1;
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esize = 16;
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}
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else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
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{
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index = 0;
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esize = 32;
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}
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else
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{
|
||||
func (stream, "<undefined index>");
|
||||
return;
|
||||
}
|
||||
|
||||
targetBeat = (op1 & 0x1) | (h << 1);
|
||||
idx = index + targetBeat * (32/esize);
|
||||
|
||||
func (stream, "%lu", idx);
|
||||
}
|
||||
|
||||
/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
|
||||
in length and integer of floating-point type. */
|
||||
static void
|
||||
print_simd_imm8 (struct disassemble_info *info, unsigned long given,
|
||||
unsigned int ibit_loc, const struct mopcode32 *insn)
|
||||
{
|
||||
int bits = 0;
|
||||
int cmode = (given >> 8) & 0xf;
|
||||
int op = (given >> 5) & 0x1;
|
||||
unsigned long value = 0, hival = 0;
|
||||
unsigned shift;
|
||||
int size = 0;
|
||||
int isfloat = 0;
|
||||
void *stream = info->stream;
|
||||
fprintf_ftype func = info->fprintf_func;
|
||||
|
||||
/* On Neon the 'i' bit is at bit 24, on mve it is
|
||||
at bit 28. */
|
||||
bits |= ((given >> ibit_loc) & 1) << 7;
|
||||
bits |= ((given >> 16) & 7) << 4;
|
||||
bits |= ((given >> 0) & 15) << 0;
|
||||
|
||||
if (cmode < 8)
|
||||
{
|
||||
shift = (cmode >> 1) & 3;
|
||||
value = (unsigned long) bits << (8 * shift);
|
||||
size = 32;
|
||||
}
|
||||
else if (cmode < 12)
|
||||
{
|
||||
shift = (cmode >> 1) & 1;
|
||||
value = (unsigned long) bits << (8 * shift);
|
||||
size = 16;
|
||||
}
|
||||
else if (cmode < 14)
|
||||
{
|
||||
shift = (cmode & 1) + 1;
|
||||
value = (unsigned long) bits << (8 * shift);
|
||||
value |= (1ul << (8 * shift)) - 1;
|
||||
size = 32;
|
||||
}
|
||||
else if (cmode == 14)
|
||||
{
|
||||
if (op)
|
||||
{
|
||||
/* Bit replication into bytes. */
|
||||
int ix;
|
||||
unsigned long mask;
|
||||
|
||||
value = 0;
|
||||
hival = 0;
|
||||
for (ix = 7; ix >= 0; ix--)
|
||||
{
|
||||
mask = ((bits >> ix) & 1) ? 0xff : 0;
|
||||
if (ix <= 3)
|
||||
value = (value << 8) | mask;
|
||||
else
|
||||
hival = (hival << 8) | mask;
|
||||
}
|
||||
size = 64;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Byte replication. */
|
||||
value = (unsigned long) bits;
|
||||
size = 8;
|
||||
}
|
||||
}
|
||||
else if (!op)
|
||||
{
|
||||
/* Floating point encoding. */
|
||||
int tmp;
|
||||
|
||||
value = (unsigned long) (bits & 0x7f) << 19;
|
||||
value |= (unsigned long) (bits & 0x80) << 24;
|
||||
tmp = bits & 0x40 ? 0x3c : 0x40;
|
||||
value |= (unsigned long) tmp << 24;
|
||||
size = 32;
|
||||
isfloat = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
func (stream, "<illegal constant %.8x:%x:%x>",
|
||||
bits, cmode, op);
|
||||
size = 32;
|
||||
return;
|
||||
}
|
||||
|
||||
// printU determines whether the immediate value should be printed as
|
||||
// unsigned.
|
||||
unsigned printU = 0;
|
||||
switch (insn->mve_op)
|
||||
{
|
||||
default:
|
||||
break;
|
||||
// We want this for instructions that don't have a 'signed' type
|
||||
case MVE_VBIC_IMM:
|
||||
case MVE_VORR_IMM:
|
||||
case MVE_VMVN_IMM:
|
||||
case MVE_VMOV_IMM_TO_VEC:
|
||||
printU = 1;
|
||||
break;
|
||||
}
|
||||
switch (size)
|
||||
{
|
||||
case 8:
|
||||
func (stream, "#%ld\t; 0x%.2lx", value, value);
|
||||
break;
|
||||
|
||||
case 16:
|
||||
func (stream,
|
||||
printU
|
||||
? "#%lu\t; 0x%.4lx"
|
||||
: "#%ld\t; 0x%.4lx", value, value);
|
||||
break;
|
||||
|
||||
case 32:
|
||||
if (isfloat)
|
||||
{
|
||||
unsigned char valbytes[4];
|
||||
double fvalue;
|
||||
|
||||
/* Do this a byte at a time so we don't have to
|
||||
worry about the host's endianness. */
|
||||
valbytes[0] = value & 0xff;
|
||||
valbytes[1] = (value >> 8) & 0xff;
|
||||
valbytes[2] = (value >> 16) & 0xff;
|
||||
valbytes[3] = (value >> 24) & 0xff;
|
||||
|
||||
floatformat_to_double
|
||||
(& floatformat_ieee_single_little, valbytes,
|
||||
& fvalue);
|
||||
|
||||
func (stream, "#%.7g\t; 0x%.8lx", fvalue,
|
||||
value);
|
||||
}
|
||||
else
|
||||
func (stream,
|
||||
printU
|
||||
? "#%lu\t; 0x%.8lx"
|
||||
: "#%ld\t; 0x%.8lx",
|
||||
(long) (((value & 0x80000000L) != 0)
|
||||
&& !printU
|
||||
? value | ~0xffffffffL : value),
|
||||
value);
|
||||
break;
|
||||
|
||||
case 64:
|
||||
func (stream, "#0x%.8lx%.8lx", hival, value);
|
||||
break;
|
||||
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static void
|
||||
print_mve_undefined (struct disassemble_info *info,
|
||||
enum mve_undefined undefined_code)
|
||||
|
|
@ -4882,6 +5340,10 @@ print_mve_undefined (struct disassemble_info *info,
|
|||
func (stream, "size equals zero");
|
||||
break;
|
||||
|
||||
case UNDEF_SIZE_2:
|
||||
func (stream, "size equals two");
|
||||
break;
|
||||
|
||||
case UNDEF_SIZE_3:
|
||||
func (stream, "size equals three");
|
||||
break;
|
||||
|
|
@ -4918,6 +5380,18 @@ print_mve_undefined (struct disassemble_info *info,
|
|||
func (stream, "fsi = 0 and invalid imm6");
|
||||
break;
|
||||
|
||||
case UNDEF_BAD_OP1_OP2:
|
||||
func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
|
||||
break;
|
||||
|
||||
case UNDEF_BAD_U_OP1_OP2:
|
||||
func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
|
||||
break;
|
||||
|
||||
case UNDEF_OP_0_BAD_CMODE:
|
||||
func (stream, "op field equal 0 and bad cmode");
|
||||
break;
|
||||
|
||||
case UNDEF_NONE:
|
||||
break;
|
||||
}
|
||||
|
|
@ -4976,6 +5450,14 @@ print_mve_unpredictable (struct disassemble_info *info,
|
|||
func (stream, "same general-purpose register used for both operands");
|
||||
break;
|
||||
|
||||
case UNPRED_Q_REGS_EQ_AND_SIZE_1:
|
||||
func (stream, "use of identical q registers and size = 1");
|
||||
break;
|
||||
|
||||
case UNPRED_Q_REGS_EQ_AND_SIZE_2:
|
||||
func (stream, "use of identical q registers and size = 1");
|
||||
break;
|
||||
|
||||
case UNPRED_NONE:
|
||||
break;
|
||||
}
|
||||
|
|
@ -5339,6 +5821,88 @@ print_mve_size (struct disassemble_info *info,
|
|||
}
|
||||
break;
|
||||
|
||||
case MVE_VMOV_GP_TO_VEC_LANE:
|
||||
case MVE_VMOV_VEC_LANE_TO_GP:
|
||||
switch (size)
|
||||
{
|
||||
case 0: case 4:
|
||||
func (stream, "32");
|
||||
break;
|
||||
|
||||
case 1: case 3:
|
||||
case 5: case 7:
|
||||
func (stream, "16");
|
||||
break;
|
||||
|
||||
case 8: case 9: case 10: case 11:
|
||||
case 12: case 13: case 14: case 15:
|
||||
func (stream, "8");
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case MVE_VMOV_IMM_TO_VEC:
|
||||
switch (size)
|
||||
{
|
||||
case 0: case 4: case 8:
|
||||
case 12: case 24: case 26:
|
||||
func (stream, "i32");
|
||||
break;
|
||||
case 16: case 20:
|
||||
func (stream, "i16");
|
||||
break;
|
||||
case 28:
|
||||
func (stream, "i8");
|
||||
break;
|
||||
case 29:
|
||||
func (stream, "i64");
|
||||
break;
|
||||
case 30:
|
||||
func (stream, "f32");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case MVE_VMVN_IMM:
|
||||
switch (size)
|
||||
{
|
||||
case 0: case 2: case 4:
|
||||
case 6: case 12: case 13:
|
||||
func (stream, "32");
|
||||
break;
|
||||
|
||||
case 8: case 10:
|
||||
func (stream, "16");
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case MVE_VBIC_IMM:
|
||||
case MVE_VORR_IMM:
|
||||
switch (size)
|
||||
{
|
||||
case 1: case 3:
|
||||
case 5: case 7:
|
||||
func (stream, "32");
|
||||
break;
|
||||
|
||||
case 9: case 11:
|
||||
func (stream, "16");
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -5563,7 +6127,6 @@ print_insn_coprocessor (bfd_vma pc,
|
|||
don't let it match here. */
|
||||
continue;
|
||||
|
||||
|
||||
for (c = insn->assembler; *c; c++)
|
||||
{
|
||||
if (*c == '%')
|
||||
|
|
@ -6830,10 +7393,30 @@ print_insn_mve (struct disassemble_info *info, long given)
|
|||
|
||||
case 'u':
|
||||
{
|
||||
if (arm_decode_field (given, 28, 28) == 0)
|
||||
func (stream, "s");
|
||||
unsigned long op1 = arm_decode_field (given, 21, 22);
|
||||
|
||||
if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
|
||||
{
|
||||
/* Check for signed. */
|
||||
if (arm_decode_field (given, 23, 23) == 0)
|
||||
{
|
||||
/* We don't print 's' for S32. */
|
||||
if ((arm_decode_field (given, 5, 6) == 0)
|
||||
&& ((op1 == 0) || (op1 == 1)))
|
||||
;
|
||||
else
|
||||
func (stream, "s");
|
||||
}
|
||||
else
|
||||
func (stream, "u");
|
||||
}
|
||||
else
|
||||
func (stream, "u");
|
||||
{
|
||||
if (arm_decode_field (given, 28, 28) == 0)
|
||||
func (stream, "s");
|
||||
else
|
||||
func (stream, "u");
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -6850,6 +7433,16 @@ print_insn_mve (struct disassemble_info *info, long given)
|
|||
print_mve_register_blocks (info, given, insn->mve_op);
|
||||
break;
|
||||
|
||||
case 'E':
|
||||
/* SIMD encoded constant for mov, mvn, vorr, vbic. */
|
||||
|
||||
print_simd_imm8 (info, given, 28, insn);
|
||||
break;
|
||||
|
||||
case 'N':
|
||||
print_mve_vmov_index (info, given);
|
||||
break;
|
||||
|
||||
case '0': case '1': case '2': case '3': case '4':
|
||||
case '5': case '6': case '7': case '8': case '9':
|
||||
{
|
||||
|
|
@ -6907,12 +7500,18 @@ print_insn_mve (struct disassemble_info *info, long given)
|
|||
func (stream, "%ld", value);
|
||||
value_in_comment = value;
|
||||
break;
|
||||
case 'F':
|
||||
func (stream, "s%ld", value);
|
||||
break;
|
||||
case 'Q':
|
||||
if (value & 0x8)
|
||||
func (stream, "<illegal reg q%ld.5>", value);
|
||||
else
|
||||
func (stream, "q%ld", value);
|
||||
break;
|
||||
case 'x':
|
||||
func (stream, "0x%08lx", value);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue