[PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new reasons. (enum mve_undefined): Likewise. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_unpredictable): Likewise. (print_mve_rounding_mode): Likewise. (print_mve_vcvt_size): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
This commit is contained in:
Andre Vieira
parent
ef1576a1b5
commit
bf0b396de7
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@ -11,7 +11,7 @@
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[^:]*:13: Error: bad type in SIMD instruction -- `vrintm.f64 q0,q1'
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[^:]*:13: Error: bad type in SIMD instruction -- `vrintp.i16 q0,q1'
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[^:]*:13: Error: bad type in SIMD instruction -- `vrintp.f64 q0,q1'
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[^:]*:14: Error: invalid rounding mode -- `vrintr.f16 q0,q1'
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[^:]*:14: Error: VFP single, double or Neon quad precision register expected -- `vrintr.f16 q0,q1'
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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@ -1,3 +1,19 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (enum mve_instructions): Add new instructions.
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(enum mve_unpredictable): Add new reasons.
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(enum mve_undefined): Likewise.
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(is_mve_encoding_conflict): Handle new instructions.
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(is_mve_undefined): Likewise.
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(is_mve_unpredictable): Likewise.
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(print_mve_undefined): Likewise.
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(print_mve_unpredictable): Likewise.
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(print_mve_rounding_mode): Likewise.
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(print_mve_vcvt_size): Likewise.
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(print_mve_size): Likewise.
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(print_insn_mve): Likewise.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -124,6 +124,11 @@ enum mve_instructions
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MVE_VSTRD_SCATTER_T4,
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MVE_VSTRW_SCATTER_T5,
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MVE_VSTRD_SCATTER_T6,
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MVE_VCVT_FP_FIX_VEC,
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MVE_VCVT_BETWEEN_FP_INT,
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MVE_VCVT_FP_HALF_FP,
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MVE_VCVT_FROM_FP_TO_INT,
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MVE_VRINT_FP,
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MVE_NONE
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};
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@ -145,12 +150,14 @@ enum mve_unpredictable
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UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
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equal. */
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UNPRED_OS, /* Unpredictable because offset scaled == 1. */
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UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
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same. */
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UNPRED_NONE /* No unpredictable behavior. */
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};
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enum mve_undefined
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{
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UNDEF_SIZE_3, /* undefined because size == 3. */
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UNDEF_SIZE_0, /* undefined because size == 0. */
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UNDEF_SIZE_3, /* undefined because size == 3. */
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UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
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UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
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@ -160,6 +167,8 @@ enum mve_undefined
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UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
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size == 1. */
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UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
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UNDEF_VCVT_IMM6, /* imm6 < 32. */
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UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
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UNDEF_NONE /* no undefined behavior. */
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};
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@ -1868,7 +1877,9 @@ static const struct opcode32 neon_opcodes[] =
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%d print addr mode of MVE vldr[bhw] and vstr[bhw]
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%u print 'U' (unsigned) or 'S' for various mve instructions
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%i print MVE predicate(s) for vpt and vpst
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%m print rounding mode for vcvt and vrint
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%n print vector comparison code for predicated instruction
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%s print size for various vcvt instructions
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%v print vector predicate for instruction in predicated
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block
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%o print offset scaled for vldr[hwd] and vstr[hwd]
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@ -1882,7 +1893,8 @@ static const struct opcode32 neon_opcodes[] =
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UNPREDICTABLE
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%<bitfield>s print size for vector predicate & non VMOV instructions
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%<bitfield>i print immediate for vstr/vldr reg +/- imm
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*/
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%<bitfield>k print immediate for vector conversion instruction
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*/
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static const struct mopcode32 mve_opcodes[] =
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{
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@ -2051,6 +2063,36 @@ static const struct mopcode32 mve_opcodes[] =
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0xef000140, 0xef811f51,
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"vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VCVT. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCVT_FP_FIX_VEC,
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0xef800c50, 0xef801cd1,
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"vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
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/* Vector VCVT. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCVT_BETWEEN_FP_INT,
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0xffb30640, 0xffb31e51,
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"vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VCVT between single and half-precision float, bottom half. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCVT_FP_HALF_FP,
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0xee3f0e01, 0xefbf1fd1,
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"vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VCVT between single and half-precision float, top half. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCVT_FP_HALF_FP,
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0xee3f1e01, 0xefbf1fd1,
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"vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VCVT. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCVT_FROM_FP_TO_INT,
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0xffb30040, 0xffb31c51,
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"vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VLD2. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLD2,
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@ -2129,6 +2171,12 @@ static const struct mopcode32 mve_opcodes[] =
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0xec101f00, 0xfe101f80,
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"vldrw%v.u32\t%13-15,22Q, %d"},
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/* Vector VRINT floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VRINT_FP,
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0xffb20440, 0xffb31c51,
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"vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VST2 no writeback. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VST2,
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@ -4269,6 +4317,9 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VCVT_FP_FIX_VEC:
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return (arm_decode_field (given, 16, 21) & 0x38) == 0;
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default:
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return FALSE;
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@ -4524,6 +4575,43 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VCVT_FP_FIX_VEC:
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{
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unsigned long imm6 = arm_decode_field (given, 16, 21);
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if ((imm6 & 0x20) == 0)
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{
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*undefined_code = UNDEF_VCVT_IMM6;
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return TRUE;
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}
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if ((arm_decode_field (given, 9, 9) == 0)
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&& ((imm6 & 0x30) == 0x20))
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{
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*undefined_code = UNDEF_VCVT_FSI_IMM6;
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return TRUE;
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}
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return FALSE;
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}
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case MVE_VCVT_BETWEEN_FP_INT:
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case MVE_VCVT_FROM_FP_TO_INT:
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{
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unsigned long size = arm_decode_field (given, 18, 19);
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if (size == 0)
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{
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*undefined_code = UNDEF_SIZE_0;
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return TRUE;
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}
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else if (size == 3)
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{
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*undefined_code = UNDEF_SIZE_3;
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return TRUE;
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}
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else
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return FALSE;
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}
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default:
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return FALSE;
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}
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@ -4749,6 +4837,31 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VCVT_BETWEEN_FP_INT:
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case MVE_VCVT_FROM_FP_TO_INT:
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{
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unsigned long rt = arm_decode_field (given, 0, 3);
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unsigned long rt2 = arm_decode_field (given, 16, 19);
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if ((rt == 0xd) || (rt2 == 0xd))
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{
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*unpredictable_code = UNPRED_R13;
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return TRUE;
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}
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else if ((rt == 0xf) || (rt2 == 0xf))
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{
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*unpredictable_code = UNPRED_R15;
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return TRUE;
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}
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else if (rt == rt2)
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{
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*unpredictable_code = UNPRED_GP_REGS_EQUAL;
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return TRUE;
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}
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return FALSE;
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}
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default:
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return FALSE;
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}
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@ -4797,6 +4910,14 @@ print_mve_undefined (struct disassemble_info *info,
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func (stream, "not unsigned");
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break;
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case UNDEF_VCVT_IMM6:
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func (stream, "invalid imm6");
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break;
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case UNDEF_VCVT_FSI_IMM6:
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func (stream, "fsi = 0 and invalid imm6");
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break;
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case UNDEF_NONE:
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break;
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}
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@ -4851,6 +4972,10 @@ print_mve_unpredictable (struct disassemble_info *info,
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func (stream, "use of offset scaled");
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break;
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case UNPRED_GP_REGS_EQUAL:
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func (stream, "same general-purpose register used for both operands");
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break;
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case UNPRED_NONE:
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break;
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}
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@ -4894,6 +5019,234 @@ print_mve_register_blocks (struct disassemble_info *info,
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}
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}
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static void
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print_mve_rounding_mode (struct disassemble_info *info,
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unsigned long given,
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enum mve_instructions matched_insn)
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{
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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switch (matched_insn)
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{
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case MVE_VCVT_FROM_FP_TO_INT:
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{
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switch (arm_decode_field (given, 8, 9))
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{
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case 0:
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func (stream, "a");
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break;
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case 1:
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func (stream, "n");
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break;
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case 2:
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func (stream, "p");
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break;
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case 3:
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func (stream, "m");
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break;
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default:
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break;
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}
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}
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break;
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case MVE_VRINT_FP:
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{
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switch (arm_decode_field (given, 7, 9))
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{
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case 0:
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func (stream, "n");
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break;
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case 1:
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func (stream, "x");
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break;
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case 2:
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func (stream, "a");
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break;
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case 3:
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func (stream, "z");
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break;
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case 5:
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func (stream, "m");
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break;
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case 7:
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func (stream, "p");
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case 4:
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case 6:
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default:
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break;
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}
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}
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break;
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default:
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break;
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}
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}
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static void
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print_mve_vcvt_size (struct disassemble_info *info,
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unsigned long given,
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enum mve_instructions matched_insn)
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{
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unsigned long mode = 0;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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switch (matched_insn)
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{
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case MVE_VCVT_FP_FIX_VEC:
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{
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mode = (((given & 0x200) >> 7)
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| ((given & 0x10000000) >> 27)
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| ((given & 0x100) >> 8));
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switch (mode)
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{
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case 0:
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func (stream, "f16.s16");
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break;
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case 1:
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func (stream, "s16.f16");
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break;
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case 2:
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func (stream, "f16.u16");
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break;
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case 3:
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func (stream, "u16.f16");
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break;
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case 4:
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func (stream, "f32.s32");
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break;
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case 5:
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func (stream, "s32.f32");
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break;
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case 6:
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func (stream, "f32.u32");
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break;
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case 7:
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func (stream, "u32.f32");
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break;
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default:
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break;
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}
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break;
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}
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case MVE_VCVT_BETWEEN_FP_INT:
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{
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unsigned long size = arm_decode_field (given, 18, 19);
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unsigned long op = arm_decode_field (given, 7, 8);
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if (size == 1)
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{
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switch (op)
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{
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case 0:
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func (stream, "f16.s16");
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break;
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case 1:
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func (stream, "f16.u16");
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break;
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case 2:
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func (stream, "s16.f16");
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break;
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case 3:
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func (stream, "u16.f16");
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break;
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default:
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break;
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}
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}
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else if (size == 2)
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{
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switch (op)
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{
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case 0:
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func (stream, "f32.s32");
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break;
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case 1:
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func (stream, "f32.u32");
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break;
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case 2:
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func (stream, "s32.f32");
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break;
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case 3:
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func (stream, "u32.f32");
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break;
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}
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}
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}
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break;
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case MVE_VCVT_FP_HALF_FP:
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{
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unsigned long op = arm_decode_field (given, 28, 28);
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if (op == 0)
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func (stream, "f16.f32");
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else if (op == 1)
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func (stream, "f32.f16");
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}
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break;
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case MVE_VCVT_FROM_FP_TO_INT:
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{
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unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
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switch (size)
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{
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case 2:
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func (stream, "s16.f16");
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break;
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case 3:
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func (stream, "u16.f16");
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break;
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case 4:
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func (stream, "s32.f32");
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break;
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case 5:
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func (stream, "u32.f32");
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break;
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default:
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break;
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}
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}
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break;
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default:
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break;
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}
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}
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static void
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print_instruction_predicate (struct disassemble_info *info)
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{
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@ -4941,6 +5294,7 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VPT_VEC_T5:
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case MVE_VPT_VEC_T6:
|
||||
case MVE_VRHADD:
|
||||
case MVE_VRINT_FP:
|
||||
case MVE_VST2:
|
||||
case MVE_VST4:
|
||||
case MVE_VSTRB_SCATTER_T1:
|
||||
|
|
@ -6466,6 +6820,14 @@ print_insn_mve (struct disassemble_info *info, long given)
|
|||
}
|
||||
break;
|
||||
|
||||
case 'm':
|
||||
print_mve_rounding_mode (info, given, insn->mve_op);
|
||||
break;
|
||||
|
||||
case 's':
|
||||
print_mve_vcvt_size (info, given, insn->mve_op);
|
||||
break;
|
||||
|
||||
case 'u':
|
||||
{
|
||||
if (arm_decode_field (given, 28, 28) == 0)
|
||||
|
|
@ -6535,6 +6897,9 @@ print_insn_mve (struct disassemble_info *info, long given)
|
|||
func (stream, "%lu", mod_imm);
|
||||
}
|
||||
break;
|
||||
case 'k':
|
||||
func (stream, "%lu", 64 - value);
|
||||
break;
|
||||
case 'r':
|
||||
func (stream, "%s", arm_regnames[value]);
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in New Issue