[PATCH 43/57][Arm][OBJDUMP] Add support for MVE instructions: scatter stores and gather loads
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new reasons. (enum mve_undefined): Likewise. (is_mve_undefined): Handle new instructions. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_unpredictable): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
This commit is contained in:
Andre Vieira
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@ -1,3 +1,16 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (enum mve_instructions): Add new instructions.
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(enum mve_unpredictable): Add new reasons.
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(enum mve_undefined): Likewise.
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(is_mve_undefined): Handle new instructions.
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(is_mve_unpredictable): Likewise.
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(print_mve_undefined): Likewise.
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(print_mve_unpredictable): Likewise.
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(print_mve_size): Likewise.
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(print_insn_mve): Likewise.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -112,6 +112,18 @@ enum mve_instructions
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MVE_VSTRB_T5,
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MVE_VSTRH_T6,
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MVE_VSTRW_T7,
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MVE_VLDRB_GATHER_T1,
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MVE_VLDRH_GATHER_T2,
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MVE_VLDRW_GATHER_T3,
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MVE_VLDRD_GATHER_T4,
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MVE_VLDRW_GATHER_T5,
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MVE_VLDRD_GATHER_T6,
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MVE_VSTRB_SCATTER_T1,
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MVE_VSTRH_SCATTER_T2,
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MVE_VSTRW_SCATTER_T3,
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MVE_VSTRD_SCATTER_T4,
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MVE_VSTRW_SCATTER_T5,
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MVE_VSTRD_SCATTER_T6,
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MVE_NONE
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};
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@ -130,6 +142,9 @@ enum mve_unpredictable
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vec reg start > 6 (vld2/st2). */
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UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
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and WB bit = 1. */
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UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
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equal. */
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UNPRED_OS, /* Unpredictable because offset scaled == 1. */
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UNPRED_NONE /* No unpredictable behavior. */
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};
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@ -138,6 +153,13 @@ enum mve_undefined
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UNDEF_SIZE_3, /* undefined because size == 3. */
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UNDEF_SIZE_3, /* undefined because size == 3. */
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UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
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UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
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UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
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UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
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size == 0. */
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UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
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size == 1. */
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UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
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UNDEF_NONE /* no undefined behavior. */
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};
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@ -1840,6 +1862,8 @@ static const struct opcode32 neon_opcodes[] =
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%% %
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%a print '+' or '-' or imm offset in vldr[bhwd] and
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vstr[bhwd]
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%c print condition code
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%d print addr mode of MVE vldr[bhw] and vstr[bhw]
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%u print 'U' (unsigned) or 'S' for various mve instructions
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@ -1847,6 +1871,7 @@ static const struct opcode32 neon_opcodes[] =
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%n print vector comparison code for predicated instruction
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%v print vector predicate for instruction in predicated
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block
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%o print offset scaled for vldr[hwd] and vstr[hwd]
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%w print writeback mode for MVE v{st,ld}[24]
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%B print v{st,ld}[24] any one operands
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@ -1856,7 +1881,8 @@ static const struct opcode32 neon_opcodes[] =
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%<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
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UNPREDICTABLE
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%<bitfield>s print size for vector predicate & non VMOV instructions
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*/
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%<bitfield>i print immediate for vstr/vldr reg +/- imm
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*/
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static const struct mopcode32 mve_opcodes[] =
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{
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@ -2037,6 +2063,42 @@ static const struct mopcode32 mve_opcodes[] =
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0xfc901e01, 0xff901e1f,
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"vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
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/* Vector VLDRB gather load. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRB_GATHER_T1,
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0xec900e00, 0xefb01e50,
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"vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
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/* Vector VLDRH gather load. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRH_GATHER_T2,
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0xec900e10, 0xefb01e50,
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"vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
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/* Vector VLDRW gather load. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRW_GATHER_T3,
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0xfc900f40, 0xffb01fd0,
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"vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
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/* Vector VLDRD gather load. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRD_GATHER_T4,
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0xec900fd0, 0xefb01fd0,
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"vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
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/* Vector VLDRW gather load. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRW_GATHER_T5,
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0xfd101e00, 0xff111f00,
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"vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
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/* Vector VLDRD gather load, variant T6. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRD_GATHER_T6,
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0xfd101f00, 0xff111f00,
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"vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
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/* Vector VLDRB. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRB_T1,
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@ -2091,6 +2153,42 @@ static const struct mopcode32 mve_opcodes[] =
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0xfca01e01, 0xffb01e1f,
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"vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
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/* Vector VSTRB scatter store, T1 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRB_SCATTER_T1,
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0xec800e00, 0xffb01e50,
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"vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
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/* Vector VSTRH scatter store, T2 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRH_SCATTER_T2,
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0xec800e10, 0xffb01e50,
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"vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
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/* Vector VSTRW scatter store, T3 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRW_SCATTER_T3,
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0xec800e40, 0xffb01e50,
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"vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
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/* Vector VSTRD scatter store, T4 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRD_SCATTER_T4,
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0xec800fd0, 0xffb01fd0,
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"vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
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/* Vector VSTRW scatter store, T5 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRW_SCATTER_T5,
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0xfd001e00, 0xff111f00,
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"vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
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/* Vector VSTRD scatter store, T6 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRD_SCATTER_T6,
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0xfd001f00, 0xff111f00,
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"vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
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/* Vector VSTRB. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRB_T1,
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@ -4319,6 +4417,113 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VLDRB_GATHER_T1:
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if (arm_decode_field (given, 7, 8) == 3)
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{
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*undefined_code = UNDEF_SIZE_3;
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return TRUE;
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}
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else if ((arm_decode_field (given, 28, 28) == 0)
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&& (arm_decode_field (given, 7, 8) == 0))
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{
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*undefined_code = UNDEF_NOT_UNS_SIZE_0;
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return TRUE;
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}
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else
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return FALSE;
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case MVE_VLDRH_GATHER_T2:
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if (arm_decode_field (given, 7, 8) == 3)
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{
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*undefined_code = UNDEF_SIZE_3;
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return TRUE;
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}
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else if ((arm_decode_field (given, 28, 28) == 0)
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&& (arm_decode_field (given, 7, 8) == 1))
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{
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*undefined_code = UNDEF_NOT_UNS_SIZE_1;
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return TRUE;
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}
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else if (arm_decode_field (given, 7, 8) == 0)
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{
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*undefined_code = UNDEF_SIZE_0;
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return TRUE;
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}
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else
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return FALSE;
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case MVE_VLDRW_GATHER_T3:
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if (arm_decode_field (given, 7, 8) != 2)
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{
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*undefined_code = UNDEF_SIZE_NOT_2;
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return TRUE;
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}
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else if (arm_decode_field (given, 28, 28) == 0)
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{
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*undefined_code = UNDEF_NOT_UNSIGNED;
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return TRUE;
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}
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else
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return FALSE;
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case MVE_VLDRD_GATHER_T4:
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if (arm_decode_field (given, 7, 8) != 3)
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{
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*undefined_code = UNDEF_SIZE_NOT_3;
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return TRUE;
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}
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else if (arm_decode_field (given, 28, 28) == 0)
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{
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*undefined_code = UNDEF_NOT_UNSIGNED;
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return TRUE;
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}
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else
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return FALSE;
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case MVE_VSTRB_SCATTER_T1:
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if (arm_decode_field (given, 7, 8) == 3)
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{
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*undefined_code = UNDEF_SIZE_3;
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return TRUE;
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}
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else
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return FALSE;
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case MVE_VSTRH_SCATTER_T2:
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{
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unsigned long size = arm_decode_field (given, 7, 8);
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if (size == 3)
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{
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*undefined_code = UNDEF_SIZE_3;
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return TRUE;
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}
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else if (size == 0)
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{
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*undefined_code = UNDEF_SIZE_0;
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return TRUE;
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}
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else
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return FALSE;
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}
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case MVE_VSTRW_SCATTER_T3:
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if (arm_decode_field (given, 7, 8) != 2)
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{
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*undefined_code = UNDEF_SIZE_NOT_2;
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return TRUE;
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}
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else
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return FALSE;
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case MVE_VSTRD_SCATTER_T4:
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if (arm_decode_field (given, 7, 8) != 3)
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{
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*undefined_code = UNDEF_SIZE_NOT_3;
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return TRUE;
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}
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else
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return FALSE;
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default:
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return FALSE;
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}
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@ -4473,6 +4678,77 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VLDRB_GATHER_T1:
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if (arm_decode_field (given, 0, 0) == 1)
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{
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*unpredictable_code = UNPRED_OS;
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return TRUE;
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}
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/* fall through. */
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/* To handle common code with T2-T4 variants. */
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case MVE_VLDRH_GATHER_T2:
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case MVE_VLDRW_GATHER_T3:
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case MVE_VLDRD_GATHER_T4:
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{
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unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
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unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
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if (qd == qm)
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{
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*unpredictable_code = UNPRED_Q_REGS_EQUAL;
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return TRUE;
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}
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if (arm_decode_field (given, 16, 19) == 0xf)
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{
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*unpredictable_code = UNPRED_R15;
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return TRUE;
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}
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return FALSE;
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}
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case MVE_VLDRW_GATHER_T5:
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case MVE_VLDRD_GATHER_T6:
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{
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unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
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unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
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if (qd == qm)
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{
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*unpredictable_code = UNPRED_Q_REGS_EQUAL;
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return TRUE;
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}
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else
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return FALSE;
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}
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case MVE_VSTRB_SCATTER_T1:
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if (arm_decode_field (given, 16, 19) == 0xf)
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{
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*unpredictable_code = UNPRED_R15;
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return TRUE;
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}
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else if (arm_decode_field (given, 0, 0) == 1)
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{
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*unpredictable_code = UNPRED_OS;
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return TRUE;
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}
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else
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return FALSE;
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case MVE_VSTRH_SCATTER_T2:
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case MVE_VSTRW_SCATTER_T3:
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case MVE_VSTRD_SCATTER_T4:
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if (arm_decode_field (given, 16, 19) == 0xf)
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{
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*unpredictable_code = UNPRED_R15;
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return TRUE;
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}
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else
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return FALSE;
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default:
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return FALSE;
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}
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@ -4501,6 +4777,26 @@ print_mve_undefined (struct disassemble_info *info,
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func (stream, "size <= 1");
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break;
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case UNDEF_SIZE_NOT_2:
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func (stream, "size not equal to 2");
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break;
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case UNDEF_SIZE_NOT_3:
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func (stream, "size not equal to 3");
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break;
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case UNDEF_NOT_UNS_SIZE_0:
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func (stream, "not unsigned and size = zero");
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break;
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case UNDEF_NOT_UNS_SIZE_1:
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func (stream, "not unsigned and size = one");
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break;
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case UNDEF_NOT_UNSIGNED:
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func (stream, "not unsigned");
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break;
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case UNDEF_NONE:
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break;
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}
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@ -4546,6 +4842,15 @@ print_mve_unpredictable (struct disassemble_info *info,
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func (stream, "use of r13 and write back");
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break;
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case UNPRED_Q_REGS_EQUAL:
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func (stream,
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"same vector register used for destination and other operand");
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break;
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case UNPRED_OS:
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func (stream, "use of offset scaled");
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break;
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case UNPRED_NONE:
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break;
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}
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@ -4623,6 +4928,10 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VHSUB_T2:
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case MVE_VLD2:
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case MVE_VLD4:
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case MVE_VLDRB_GATHER_T1:
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case MVE_VLDRH_GATHER_T2:
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case MVE_VLDRW_GATHER_T3:
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case MVE_VLDRD_GATHER_T4:
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case MVE_VLDRB_T1:
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case MVE_VLDRH_T2:
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case MVE_VPT_VEC_T1:
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@ -4634,6 +4943,9 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VRHADD:
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case MVE_VST2:
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case MVE_VST4:
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case MVE_VSTRB_SCATTER_T1:
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case MVE_VSTRH_SCATTER_T2:
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case MVE_VSTRW_SCATTER_T3:
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case MVE_VSTRB_T1:
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case MVE_VSTRH_T2:
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if (size <= 3)
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@ -6117,6 +6429,12 @@ print_insn_mve (struct disassemble_info *info, long given)
|
||||
func (stream, "%%");
|
||||
break;
|
||||
|
||||
case 'a':
|
||||
/* Don't print anything for '+' as it is implied. */
|
||||
if (arm_decode_field (given, 23, 23) == 0)
|
||||
func (stream, "-");
|
||||
break;
|
||||
|
||||
case 'c':
|
||||
if (ifthen_state)
|
||||
func (stream, "%s", arm_conditional[IFTHEN_COND]);
|
||||
@ -6137,6 +6455,17 @@ print_insn_mve (struct disassemble_info *info, long given)
|
||||
print_vec_condition (info, given, insn->mve_op);
|
||||
break;
|
||||
|
||||
case 'o':
|
||||
if (arm_decode_field (given, 0, 0) == 1)
|
||||
{
|
||||
unsigned long size
|
||||
= arm_decode_field (given, 4, 4)
|
||||
| (arm_decode_field (given, 6, 6) << 1);
|
||||
|
||||
func (stream, ", uxtw #%lu", size);
|
||||
}
|
||||
break;
|
||||
|
||||
case 'u':
|
||||
{
|
||||
if (arm_decode_field (given, 28, 28) == 0)
|
||||
@ -6144,6 +6473,7 @@ print_insn_mve (struct disassemble_info *info, long given)
|
||||
else
|
||||
func (stream, "u");
|
||||
}
|
||||
break;
|
||||
|
||||
case 'v':
|
||||
print_instruction_predicate (info);
|
||||
@ -6181,6 +6511,30 @@ print_insn_mve (struct disassemble_info *info, long given)
|
||||
value,
|
||||
insn->mve_op);
|
||||
break;
|
||||
case 'i':
|
||||
{
|
||||
unsigned long imm
|
||||
= arm_decode_field (given, 0, 6);
|
||||
unsigned long mod_imm = imm;
|
||||
|
||||
switch (insn->mve_op)
|
||||
{
|
||||
case MVE_VLDRW_GATHER_T5:
|
||||
case MVE_VSTRW_SCATTER_T5:
|
||||
mod_imm = mod_imm << 2;
|
||||
break;
|
||||
case MVE_VSTRD_SCATTER_T6:
|
||||
case MVE_VLDRD_GATHER_T6:
|
||||
mod_imm = mod_imm << 3;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
func (stream, "%lu", mod_imm);
|
||||
}
|
||||
break;
|
||||
case 'r':
|
||||
func (stream, "%s", arm_regnames[value]);
|
||||
break;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user