[PATCH 42/57][Arm][OBJDUMP] Add support for MVE instructions: vldr[bhw] and vstr[bhw]
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_undefined): Add new reasons. (insns): Add new instructions. (is_mve_encoding_conflict): (print_mve_vld_str_addr): New print function. (is_mve_undefined): Handle new instructions. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_size): Likewise. (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions. (print_insn_mve): Handle new operands.
This commit is contained in:
Andre Vieira
parent
04d54ace12
commit
aef6d00658
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@ -1,3 +1,18 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (enum mve_instructions): Add new instructions.
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(enum mve_undefined): Add new reasons.
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(insns): Add new instructions.
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(is_mve_encoding_conflict):
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(print_mve_vld_str_addr): New print function.
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(is_mve_undefined): Handle new instructions.
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(is_mve_unpredictable): Likewise.
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(print_mve_undefined): Likewise.
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(print_mve_size): Likewise.
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(print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
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(print_insn_mve): Handle new operands.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -102,6 +102,16 @@ enum mve_instructions
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MVE_VLD4,
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MVE_VST2,
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MVE_VST4,
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MVE_VLDRB_T1,
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MVE_VLDRH_T2,
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MVE_VLDRB_T5,
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MVE_VLDRH_T6,
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MVE_VLDRW_T7,
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MVE_VSTRB_T1,
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MVE_VSTRH_T2,
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MVE_VSTRB_T5,
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MVE_VSTRH_T6,
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MVE_VSTRW_T7,
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MVE_NONE
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};
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@ -126,6 +136,8 @@ enum mve_unpredictable
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enum mve_undefined
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{
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UNDEF_SIZE_3, /* undefined because size == 3. */
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UNDEF_SIZE_3, /* undefined because size == 3. */
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UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
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UNDEF_NONE /* no undefined behavior. */
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};
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@ -1829,6 +1841,8 @@ static const struct opcode32 neon_opcodes[] =
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%% %
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%c print condition code
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%d print addr mode of MVE vldr[bhw] and vstr[bhw]
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%u print 'U' (unsigned) or 'S' for various mve instructions
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%i print MVE predicate(s) for vpt and vpst
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%n print vector comparison code for predicated instruction
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%v print vector predicate for instruction in predicated
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@ -2023,6 +2037,36 @@ static const struct mopcode32 mve_opcodes[] =
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0xfc901e01, 0xff901e1f,
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"vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
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/* Vector VLDRB. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRB_T1,
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0xec100e00, 0xee581e00,
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"vldrb%v.%u%7-8s\t%13-15Q, %d"},
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/* Vector VLDRH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRH_T2,
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0xec180e00, 0xee581e00,
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"vldrh%v.%u%7-8s\t%13-15Q, %d"},
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/* Vector VLDRB unsigned, variant T5. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRB_T5,
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0xec101e00, 0xfe101f80,
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"vldrb%v.u8\t%13-15,22Q, %d"},
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/* Vector VLDRH unsigned, variant T6. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRH_T6,
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0xec101e80, 0xfe101f80,
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"vldrh%v.u16\t%13-15,22Q, %d"},
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/* Vector VLDRW unsigned, variant T7. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VLDRW_T7,
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0xec101f00, 0xfe101f80,
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"vldrw%v.u32\t%13-15,22Q, %d"},
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/* Vector VST2 no writeback. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VST2,
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@ -2047,6 +2091,36 @@ static const struct mopcode32 mve_opcodes[] =
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0xfca01e01, 0xffb01e1f,
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"vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
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/* Vector VSTRB. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRB_T1,
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0xec000e00, 0xfe581e00,
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"vstrb%v.%7-8s\t%13-15Q, %d"},
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/* Vector VSTRH. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRH_T2,
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0xec080e00, 0xfe581e00,
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"vstrh%v.%7-8s\t%13-15Q, %d"},
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/* Vector VSTRB variant T5. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRB_T5,
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0xec001e00, 0xfe101f80,
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"vstrb%v.8\t%13-15,22Q, %d"},
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/* Vector VSTRH variant T6. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRH_T6,
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0xec001e80, 0xfe101f80,
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"vstrh%v.16\t%13-15,22Q, %d"},
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/* Vector VSTRW variant T7. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSTRW_T7,
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0xec001f00, 0xfe101f80,
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"vstrw%v.32\t%13-15,22Q, %d"},
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{ARM_FEATURE_CORE_LOW (0),
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MVE_NONE,
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0x00000000, 0x00000000, 0}
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@ -4074,12 +4148,109 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VSTRB_T1:
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case MVE_VSTRH_T2:
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if ((arm_decode_field (given, 24, 24) == 0)
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&& (arm_decode_field (given, 21, 21) == 0))
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{
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return TRUE;
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}
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else if ((arm_decode_field (given, 7, 8) == 3))
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return TRUE;
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else
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return FALSE;
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case MVE_VSTRB_T5:
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case MVE_VSTRH_T6:
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case MVE_VSTRW_T7:
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if ((arm_decode_field (given, 24, 24) == 0)
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&& (arm_decode_field (given, 21, 21) == 0))
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{
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return TRUE;
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}
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else
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return FALSE;
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default:
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return FALSE;
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}
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}
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static void
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print_mve_vld_str_addr (struct disassemble_info *info,
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unsigned long given,
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enum mve_instructions matched_insn)
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{
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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unsigned long p, w, gpr, imm, add, mod_imm;
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imm = arm_decode_field (given, 0, 6);
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mod_imm = imm;
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switch (matched_insn)
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{
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case MVE_VLDRB_T1:
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case MVE_VSTRB_T1:
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gpr = arm_decode_field (given, 16, 18);
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break;
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case MVE_VLDRH_T2:
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case MVE_VSTRH_T2:
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gpr = arm_decode_field (given, 16, 18);
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mod_imm = imm << 1;
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break;
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case MVE_VLDRH_T6:
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case MVE_VSTRH_T6:
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gpr = arm_decode_field (given, 16, 19);
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mod_imm = imm << 1;
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break;
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case MVE_VLDRW_T7:
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case MVE_VSTRW_T7:
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gpr = arm_decode_field (given, 16, 19);
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mod_imm = imm << 2;
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break;
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case MVE_VLDRB_T5:
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case MVE_VSTRB_T5:
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gpr = arm_decode_field (given, 16, 19);
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break;
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default:
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return;
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}
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p = arm_decode_field (given, 24, 24);
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w = arm_decode_field (given, 21, 21);
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add = arm_decode_field (given, 23, 23);
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char * add_sub;
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/* Don't print anything for '+' as it is implied. */
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if (add == 1)
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add_sub = "";
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else
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add_sub = "-";
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if (p == 1)
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{
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/* Offset mode. */
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if (w == 0)
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func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
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/* Pre-indexed mode. */
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else
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func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
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}
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else if ((p == 0) && (w == 1))
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/* Post-index mode. */
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func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
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}
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/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
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Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
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this encoding is undefined. */
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@ -4112,6 +4283,42 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VLDRB_T1:
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if (arm_decode_field (given, 7, 8) == 3)
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{
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*undefined_code = UNDEF_SIZE_3;
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return TRUE;
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}
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else
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return FALSE;
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case MVE_VLDRH_T2:
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if (arm_decode_field (given, 7, 8) <= 1)
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{
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*undefined_code = UNDEF_SIZE_LE_1;
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return TRUE;
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}
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else
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return FALSE;
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case MVE_VSTRB_T1:
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if ((arm_decode_field (given, 7, 8) == 0))
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{
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*undefined_code = UNDEF_SIZE_0;
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return TRUE;
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}
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else
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return FALSE;
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case MVE_VSTRH_T2:
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if ((arm_decode_field (given, 7, 8) <= 1))
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{
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*undefined_code = UNDEF_SIZE_LE_1;
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return TRUE;
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}
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else
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return FALSE;
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default:
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return FALSE;
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}
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@ -4243,6 +4450,29 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VLDRB_T5:
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case MVE_VLDRH_T6:
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case MVE_VLDRW_T7:
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case MVE_VSTRB_T5:
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case MVE_VSTRH_T6:
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case MVE_VSTRW_T7:
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{
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unsigned long rn = arm_decode_field (given, 16, 19);
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if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
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{
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*unpredictable_code = UNPRED_R13_AND_WB;
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return TRUE;
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}
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else if (rn == 0xf)
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{
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*unpredictable_code = UNPRED_R15;
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return TRUE;
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}
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else
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return FALSE;
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}
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default:
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return FALSE;
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}
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@ -4259,10 +4489,18 @@ print_mve_undefined (struct disassemble_info *info,
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switch (undefined_code)
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{
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case UNDEF_SIZE_0:
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func (stream, "size equals zero");
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break;
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case UNDEF_SIZE_3:
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func (stream, "size equals three");
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break;
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case UNDEF_SIZE_LE_1:
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func (stream, "size <= 1");
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break;
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case UNDEF_NONE:
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break;
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}
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@ -4385,6 +4623,8 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VHSUB_T2:
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case MVE_VLD2:
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case MVE_VLD4:
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case MVE_VLDRB_T1:
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case MVE_VLDRH_T2:
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case MVE_VPT_VEC_T1:
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case MVE_VPT_VEC_T2:
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case MVE_VPT_VEC_T3:
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@ -4394,6 +4634,8 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VRHADD:
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case MVE_VST2:
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case MVE_VST4:
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case MVE_VSTRB_T1:
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case MVE_VSTRH_T2:
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if (size <= 3)
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func (stream, "%s", mve_vec_sizename[size]);
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else
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@ -4646,6 +4888,15 @@ print_insn_coprocessor (bfd_vma pc,
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&& (cp_num == 8 || cp_num == 14 || cp_num == 15))
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continue;
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}
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else if ((insn->value == 0xec100f80 /* vldr (system register) */
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|| insn->value == 0xec000f80) /* vstr (system register) */
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&& arm_decode_field (given, 24, 24) == 0
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&& arm_decode_field (given, 21, 21) == 0)
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/* If the P and W bits are both 0 then these encodings match the MVE
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VLDR and VSTR instructions, these are in a different table, so we
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don't let it match here. */
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continue;
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for (c = insn->assembler; *c; c++)
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{
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@ -5871,6 +6122,10 @@ print_insn_mve (struct disassemble_info *info, long given)
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func (stream, "%s", arm_conditional[IFTHEN_COND]);
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break;
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case 'd':
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print_mve_vld_str_addr (info, given, insn->mve_op);
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break;
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case 'i':
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{
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long mve_mask = mve_extract_pred_mask (given);
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@ -5882,6 +6137,14 @@ print_insn_mve (struct disassemble_info *info, long given)
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print_vec_condition (info, given, insn->mve_op);
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break;
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case 'u':
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{
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if (arm_decode_field (given, 28, 28) == 0)
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func (stream, "s");
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else
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func (stream, "u");
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}
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case 'v':
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print_instruction_predicate (info);
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break;
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