[PATCH 25/57][Arm][GAS] Add support for MVE instruction: vmvn, vqabs and vqneg
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_mvn): Change to accept MVE variants. (do_neon_sat_abs_neg): Likewise. (insns): Likewise. * testsuite/gas/arm/mve-vmvn-bad.d: New test. * testsuite/gas/arm/mve-vmvn-bad.l: New test. * testsuite/gas/arm/mve-vmvn-bad.s: New test. * testsuite/gas/arm/mve-vqabsneg-bad.d: New test. * testsuite/gas/arm/mve-vqabsneg-bad.l: New test. * testsuite/gas/arm/mve-vqabsneg-bad.s: New test.
This commit is contained in:
Andre Vieira
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2d78f95bb6
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1a186d296c
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@ -1,3 +1,15 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_neon_mvn): Change to accept MVE variants.
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(do_neon_sat_abs_neg): Likewise.
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(insns): Likewise.
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* testsuite/gas/arm/mve-vmvn-bad.d: New test.
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* testsuite/gas/arm/mve-vmvn-bad.l: New test.
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* testsuite/gas/arm/mve-vmvn-bad.s: New test.
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* testsuite/gas/arm/mve-vqabsneg-bad.d: New test.
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* testsuite/gas/arm/mve-vqabsneg-bad.l: New test.
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* testsuite/gas/arm/mve-vqabsneg-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_mve_vmlas): New encoding function.
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@ -18486,9 +18486,16 @@ neon_move_immediate (void)
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static void
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do_neon_mvn (void)
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{
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if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
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return;
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if (inst.operands[1].isreg)
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{
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enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
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enum neon_shape rs;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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rs = neon_select_shape (NS_QQ, NS_NULL);
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else
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rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
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NEON_ENCODE (INTEGER, inst);
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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@ -18504,6 +18511,13 @@ do_neon_mvn (void)
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}
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neon_dp_fixup (&inst);
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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{
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constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU);
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constraint ((inst.instruction & 0xd00) == 0xd00,
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_("immediate value out of range"));
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}
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}
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/* Encode instructions of form:
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@ -19450,7 +19464,14 @@ do_neon_zip_uzp (void)
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static void
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do_neon_sat_abs_neg (void)
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{
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enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
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if (check_simd_pred_availability (0, NEON_CHECK_CC | NEON_CHECK_ARCH))
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return;
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enum neon_shape rs;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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rs = neon_select_shape (NS_QQ, NS_NULL);
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else
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rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
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struct neon_type_el et = neon_check_type (2, rs,
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N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
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neon_two_same (neon_quad (rs), 1, et.size);
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@ -24057,7 +24078,6 @@ static const struct asm_opcode insns[] =
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/* CVT with optional immediate for fixed-point variant. */
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nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
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nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
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nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
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/* Data processing, three registers of different lengths. */
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@ -24111,9 +24131,7 @@ static const struct asm_opcode insns[] =
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NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
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NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
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/* VQABS / VQNEG. Types S8 S16 S32. */
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NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
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NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
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NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
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NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
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/* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
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NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
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@ -24774,6 +24792,9 @@ static const struct asm_opcode insns[] =
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mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
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MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
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MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
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mnUF(vmvn, _vmvn, 2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn),
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MNUF(vqabs, 1b00700, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
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MNUF(vqneg, 1b00780, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
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#undef ARM_VARIANT
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#define ARM_VARIANT & arm_ext_v8_3
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@ -0,0 +1,5 @@
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#name: bad MVE VMVN instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vmvn-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,20 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: invalid instruction shape -- `vmvn.i16 d0,d1'
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[^:]*:11: Error: immediate out of range -- `vmvn.i32 q0,#0x1ef'
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Error: syntax error -- `vmvneq q0,q1'
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[^:]*:16: Error: syntax error -- `vmvneq q0,q1'
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[^:]*:18: Error: syntax error -- `vmvneq q0,q1'
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[^:]*:19: Error: vector predicated instruction should be in VPT/VPST block -- `vmvnt q0,q1'
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[^:]*:21: Error: instruction missing MVE vector predication code -- `vmvn q0,q1'
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@ -0,0 +1,21 @@
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.macro cond lastop
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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vmvn.i16 q0, \lastop
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.endr
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.endm
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.syntax unified
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.thumb
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vmvn.i16 d0, d1
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vmvn.i32 q0, #0x1ef
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cond q1
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cond #0
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it eq
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vmvneq q0, q1
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vmvneq q0, q1
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vpst
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vmvneq q0, q1
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vmvnt q0, q1
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vpst
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vmvn q0, q1
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@ -0,0 +1,5 @@
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#name: bad MVE VQABS and VQNEG instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vqabsneg-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,27 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vqabs.u8 q0,q1'
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[^:]*:11: Error: bad type in SIMD instruction -- `vqneg.u16 q0,q1'
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[^:]*:12: Error: bad type in SIMD instruction -- `vqabs.s64 q0,q1'
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[^:]*:13: Error: bad instruction `vqnegs.s64 q0,q1'
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Error: syntax error -- `vqabseq.s32 q0,q1'
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[^:]*:18: Error: syntax error -- `vqabseq.s32 q0,q1'
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[^:]*:19: Error: syntax error -- `vqabseq.s32 q0,q1'
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[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vqabst.s32 q0,q1'
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[^:]*:22: Error: instruction missing MVE vector predication code -- `vqabs.s32 q0,q1'
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[^:]*:24: Error: syntax error -- `vqnegeq.s32 q0,q1'
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[^:]*:25: Error: syntax error -- `vqnegeq.s32 q0,q1'
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[^:]*:26: Error: syntax error -- `vqnegeq.s32 q0,q1'
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[^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vqnegt.s32 q0,q1'
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[^:]*:29: Error: instruction missing MVE vector predication code -- `vqneg.s32 q0,q1'
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@ -0,0 +1,29 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s16 q0, q1
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.endr
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.endm
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.syntax unified
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.thumb
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vqabs.u8 q0, q1
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vqneg.u16 q0, q1
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vqabs.s64 q0, q1
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vqnegs.s64 q0, q1
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cond vqabs
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cond vqneg
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it eq
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vqabseq.s32 q0, q1
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vqabseq.s32 q0, q1
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vqabseq.s32 q0, q1
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vqabst.s32 q0, q1
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vpst
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vqabs.s32 q0, q1
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it eq
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vqnegeq.s32 q0, q1
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vqnegeq.s32 q0, q1
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vqnegeq.s32 q0, q1
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vqnegt.s32 q0, q1
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vpst
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vqneg.s32 q0, q1
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