[PATCH 30/57][Arm][GAS] Add support for MVE instructions: vqmovnt, vqmovnb, vqmovunt, vqmovunb, vqrshl and vrshl
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vqmovnt, M_MNEM_vqmovnb, M_MNEM_vqmovunt, M_MNEM_vqmovunb): New instruction encodings. (do_mve_vqmovn): New encoding function. (do_neon_rshl): Change to accepte MVE variants. (insns): Change entries and add new for MVE mnemonics. * testsuite/gas/arm/mve-vqmovn-bad.d: New test. * testsuite/gas/arm/mve-vqmovn-bad.l: New test. * testsuite/gas/arm/mve-vqmovn-bad.s: New test. * testsuite/gas/arm/mve-vqrshl-bad.d: New test. * testsuite/gas/arm/mve-vqrshl-bad.l: New test. * testsuite/gas/arm/mve-vqrshl-bad.s: New test. * testsuite/gas/arm/mve-vrshl-bad.d: New test. * testsuite/gas/arm/mve-vrshl-bad.l: New test. * testsuite/gas/arm/mve-vrshl-bad.s: New test.
This commit is contained in:
Andre Vieira
parent
35d1cfc200
commit
1be7aba392
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@ -1,3 +1,20 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (M_MNEM_vqmovnt, M_MNEM_vqmovnb,
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M_MNEM_vqmovunt, M_MNEM_vqmovunb): New instruction encodings.
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(do_mve_vqmovn): New encoding function.
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(do_neon_rshl): Change to accepte MVE variants.
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(insns): Change entries and add new for MVE mnemonics.
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* testsuite/gas/arm/mve-vqmovn-bad.d: New test.
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* testsuite/gas/arm/mve-vqmovn-bad.l: New test.
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* testsuite/gas/arm/mve-vqmovn-bad.s: New test.
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* testsuite/gas/arm/mve-vqrshl-bad.d: New test.
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* testsuite/gas/arm/mve-vqrshl-bad.l: New test.
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* testsuite/gas/arm/mve-vqrshl-bad.s: New test.
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* testsuite/gas/arm/mve-vrshl-bad.d: New test.
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* testsuite/gas/arm/mve-vrshl-bad.l: New test.
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* testsuite/gas/arm/mve-vrshl-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum operand_parse_code): Add new operand.
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@ -14202,6 +14202,10 @@ do_t_loloop (void)
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#define M_MNEM_vrmlsldavha 0xfe800e21
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#define M_MNEM_vrmlsldavhx 0xfe801e01
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#define M_MNEM_vrmlsldavhax 0xfe801e21
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#define M_MNEM_vqmovnt 0xee331e01
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#define M_MNEM_vqmovnb 0xee330e01
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#define M_MNEM_vqmovunt 0xee311e81
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#define M_MNEM_vqmovunb 0xee310e81
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/* Neon instruction encoder helpers. */
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@ -15746,6 +15750,31 @@ do_mve_vmlas (void)
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inst.is_neon = 1;
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}
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static void
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do_mve_vqmovn (void)
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{
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struct neon_type_el et;
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if (inst.instruction == M_MNEM_vqmovnt
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|| inst.instruction == M_MNEM_vqmovnb)
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et = neon_check_type (2, NS_QQ, N_EQK,
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N_U16 | N_U32 | N_S16 | N_S32 | N_KEY);
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else
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et = neon_check_type (2, NS_QQ, N_EQK, N_S16 | N_S32 | N_KEY);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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inst.instruction |= (et.type == NT_unsigned) << 28;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= (et.size == 32) << 18;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[1].reg) << 5;
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inst.instruction |= LOW4 (inst.operands[1].reg);
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inst.is_neon = 1;
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}
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static void
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do_mve_vpsel (void)
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{
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@ -16353,15 +16382,55 @@ do_neon_qshl_imm (void)
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static void
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do_neon_rshl (void)
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{
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enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_SU_ALL | N_KEY);
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if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
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return;
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enum neon_shape rs;
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struct neon_type_el et;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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{
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rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
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et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
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}
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else
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{
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rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
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et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
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}
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unsigned int tmp;
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tmp = inst.operands[2].reg;
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inst.operands[2].reg = inst.operands[1].reg;
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inst.operands[1].reg = tmp;
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neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
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if (rs == NS_QQR)
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{
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if (inst.operands[2].reg == REG_PC)
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as_tsktsk (MVE_BAD_PC);
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else if (inst.operands[2].reg == REG_SP)
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as_tsktsk (MVE_BAD_SP);
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constraint (inst.operands[0].reg != inst.operands[1].reg,
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_("invalid instruction shape"));
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if (inst.instruction == 0x0000510)
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/* We are dealing with vqrshl. */
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inst.instruction = 0xee331ee0;
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else
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/* We are dealing with vrshl. */
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inst.instruction = 0xee331e60;
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inst.instruction |= (et.type == NT_unsigned) << 28;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= neon_logbits (et.size) << 18;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= inst.operands[2].reg;
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inst.is_neon = 1;
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}
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else
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{
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tmp = inst.operands[2].reg;
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inst.operands[2].reg = inst.operands[1].reg;
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inst.operands[1].reg = tmp;
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neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
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}
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}
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static int
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@ -24110,9 +24179,7 @@ static const struct asm_opcode insns[] =
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/* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
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NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
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NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
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NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
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NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
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NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
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NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
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/* If not immediate, fall back to neon_dyadic_i64_su.
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shl_imm should accept I8 I16 I32 I64,
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@ -24874,6 +24941,10 @@ static const struct asm_opcode insns[] =
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mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah),
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mToC("vqdmullt", ee301f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
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mToC("vqdmullb", ee300f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
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mCEF(vqmovnt, _vqmovnt, 2, (RMQ, RMQ), mve_vqmovn),
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mCEF(vqmovnb, _vqmovnb, 2, (RMQ, RMQ), mve_vqmovn),
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mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn),
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mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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@ -24960,6 +25031,8 @@ static const struct asm_opcode insns[] =
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mnUF(vqrdmlah, _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah),
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mnUF(vqdmulh, _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
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mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
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MNUF(vqrshl, 0000510, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
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MNUF(vrshl, 0000500, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
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#undef ARM_VARIANT
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#define ARM_VARIANT & arm_ext_v8_3
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@ -0,0 +1,5 @@
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#name: bad MVE VQMOVNT and VQMOVNB instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vqmovn-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,61 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vqmovnt.s8 q0,q1'
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[^:]*:11: Error: bad type in SIMD instruction -- `vqmovnt.s64 q0,q1'
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[^:]*:12: Error: bad type in SIMD instruction -- `vqmovnt.i16 q0,q1'
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[^:]*:13: Error: bad type in SIMD instruction -- `vqmovnb.u8 q0,q1'
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[^:]*:14: Error: bad type in SIMD instruction -- `vqmovnb.u64 q0,q1'
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[^:]*:15: Error: bad type in SIMD instruction -- `vqmovnb.i16 q0,q1'
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[^:]*:16: Error: bad type in SIMD instruction -- `vqmovunt.s8 q0,q1'
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[^:]*:17: Error: bad type in SIMD instruction -- `vqmovunt.s64 q0,q1'
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[^:]*:18: Error: bad type in SIMD instruction -- `vqmovunt.i16 q0,q1'
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[^:]*:19: Error: bad type in SIMD instruction -- `vqmovunb.s8 q0,q1'
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[^:]*:20: Error: bad type in SIMD instruction -- `vqmovunb.s64 q0,q1'
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[^:]*:21: Error: bad type in SIMD instruction -- `vqmovunb.i16 q0,q1'
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[^:]*:22: Error: bad type in SIMD instruction -- `vqmovunt.u16 q0,q1'
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[^:]*:23: Error: bad type in SIMD instruction -- `vqmovunt.u32 q0,q1'
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[^:]*:24: Error: bad type in SIMD instruction -- `vqmovunb.u16 q0,q1'
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[^:]*:25: Error: bad type in SIMD instruction -- `vqmovunb.u32 q0,q1'
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:31: Error: syntax error -- `vqmovnteq.s16 q0,q1'
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[^:]*:32: Error: syntax error -- `vqmovnteq.s16 q0,q1'
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[^:]*:34: Error: syntax error -- `vqmovnteq.s16 q0,q1'
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[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqmovntt.s16 q0,q1'
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[^:]*:37: Error: instruction missing MVE vector predication code -- `vqmovnt.s16 q0,q1'
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[^:]*:39: Error: syntax error -- `vqmovnbeq.s16 q0,q1'
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[^:]*:40: Error: syntax error -- `vqmovnbeq.s16 q0,q1'
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[^:]*:42: Error: syntax error -- `vqmovnbeq.s16 q0,q1'
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[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqmovnbt.s16 q0,q1'
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[^:]*:45: Error: instruction missing MVE vector predication code -- `vqmovnb.s16 q0,q1'
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[^:]*:47: Error: syntax error -- `vqmovunteq.s16 q0,q1'
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[^:]*:48: Error: syntax error -- `vqmovunteq.s16 q0,q1'
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[^:]*:50: Error: syntax error -- `vqmovunteq.s16 q0,q1'
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[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqmovuntt.s16 q0,q1'
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[^:]*:53: Error: instruction missing MVE vector predication code -- `vqmovunt.s16 q0,q1'
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[^:]*:55: Error: syntax error -- `vqmovunbeq.s16 q0,q1'
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[^:]*:56: Error: syntax error -- `vqmovunbeq.s16 q0,q1'
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[^:]*:58: Error: syntax error -- `vqmovunbeq.s16 q0,q1'
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[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqmovunbt.s16 q0,q1'
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[^:]*:61: Error: instruction missing MVE vector predication code -- `vqmovunb.s16 q0,q1'
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@ -0,0 +1,61 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s16 q0, q1
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.endr
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.endm
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.syntax unified
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.thumb
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vqmovnt.s8 q0, q1
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vqmovnt.s64 q0, q1
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vqmovnt.i16 q0, q1
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vqmovnb.u8 q0, q1
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vqmovnb.u64 q0, q1
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vqmovnb.i16 q0, q1
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vqmovunt.s8 q0, q1
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vqmovunt.s64 q0, q1
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vqmovunt.i16 q0, q1
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vqmovunb.s8 q0, q1
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vqmovunb.s64 q0, q1
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vqmovunb.i16 q0, q1
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vqmovunt.u16 q0, q1
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vqmovunt.u32 q0, q1
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vqmovunb.u16 q0, q1
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vqmovunb.u32 q0, q1
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cond vqmovnt
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cond vqmovnb
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cond vqmovunt
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cond vqmovunb
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it eq
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vqmovnteq.s16 q0, q1
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vqmovnteq.s16 q0, q1
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vpst
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vqmovnteq.s16 q0, q1
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vqmovntt.s16 q0, q1
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vpst
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vqmovnt.s16 q0, q1
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it eq
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vqmovnbeq.s16 q0, q1
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vqmovnbeq.s16 q0, q1
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vpst
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vqmovnbeq.s16 q0, q1
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vqmovnbt.s16 q0, q1
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vpst
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vqmovnb.s16 q0, q1
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it eq
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vqmovunteq.s16 q0, q1
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vqmovunteq.s16 q0, q1
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vpst
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vqmovunteq.s16 q0, q1
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vqmovuntt.s16 q0, q1
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vpst
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vqmovunt.s16 q0, q1
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it eq
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vqmovunbeq.s16 q0, q1
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vqmovunbeq.s16 q0, q1
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vpst
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vqmovunbeq.s16 q0, q1
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vqmovunbt.s16 q0, q1
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vpst
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vqmovunb.s16 q0, q1
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@ -0,0 +1,5 @@
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#name: bad MVE VQRSHL instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vqrshl-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,32 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,q1,q2'
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[^:]*:11: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,q1,q2'
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[^:]*:12: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,q1,q2'
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[^:]*:13: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,r2'
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[^:]*:14: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,r2'
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[^:]*:15: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,r2'
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[^:]*:16: Error: invalid instruction shape -- `vqrshl.s32 q0,q1,r2'
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[^:]*:17: Warning: instruction is UNPREDICTABLE with PC operand
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[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
|
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[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:22: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
|
||||
[^:]*:23: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
|
||||
[^:]*:25: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
|
||||
[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshlt.s32 q0,q1,q2'
|
||||
[^:]*:28: Error: instruction missing MVE vector predication code -- `vqrshl.s32 q0,q1,q2'
|
||||
[^:]*:30: Error: syntax error -- `vqrshleq.s32 q0,r2'
|
||||
[^:]*:31: Error: syntax error -- `vqrshleq.s32 q0,r2'
|
||||
[^:]*:33: Error: syntax error -- `vqrshleq.s32 q0,r2'
|
||||
[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshlt.s32 q0,r2'
|
||||
[^:]*:36: Error: instruction missing MVE vector predication code -- `vqrshl.s32 q0,r2'
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
.macro cond lastreg
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
vqrshl.s16 q0, q0, \lastreg
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vqrshl.s64 q0, q1, q2
|
||||
vqrshl.u64 q0, q1, q2
|
||||
vqrshl.i32 q0, q1, q2
|
||||
vqrshl.s64 q0, r2
|
||||
vqrshl.u64 q0, r2
|
||||
vqrshl.i32 q0, r2
|
||||
vqrshl.s32 q0, q1, r2
|
||||
vqrshl.s32 q0, pc
|
||||
vqrshl.s32 q0, sp
|
||||
cond q2
|
||||
cond r2
|
||||
it eq
|
||||
vqrshleq.s32 q0, q1, q2
|
||||
vqrshleq.s32 q0, q1, q2
|
||||
vpst
|
||||
vqrshleq.s32 q0, q1, q2
|
||||
vqrshlt.s32 q0, q1, q2
|
||||
vpst
|
||||
vqrshl.s32 q0, q1, q2
|
||||
it eq
|
||||
vqrshleq.s32 q0, r2
|
||||
vqrshleq.s32 q0, r2
|
||||
vpst
|
||||
vqrshleq.s32 q0, r2
|
||||
vqrshlt.s32 q0, r2
|
||||
vpst
|
||||
vqrshl.s32 q0, r2
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#name: bad MVE VRSHL instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vrshl-bad.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Error: bad type in SIMD instruction -- `vrshl.i16 q0,q1,q2'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vrshl.i16 q0,r2'
|
||||
[^:]*:12: Error: bad type in SIMD instruction -- `vrshl.s64 q0,q1,q2'
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vrshl.s64 q0,r2'
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE with PC operand
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:19: Error: syntax error -- `vrshleq.s32 q0,q1,q2'
|
||||
[^:]*:20: Error: syntax error -- `vrshleq.s32 q0,q1,q2'
|
||||
[^:]*:22: Error: syntax error -- `vrshleq.s32 q0,q1,q2'
|
||||
[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vrshlt.s32 q0,q1,q2'
|
||||
[^:]*:25: Error: instruction missing MVE vector predication code -- `vrshl.s32 q0,q1,q2'
|
||||
[^:]*:27: Error: syntax error -- `vrshleq.s32 q0,r2'
|
||||
[^:]*:28: Error: syntax error -- `vrshleq.s32 q0,r2'
|
||||
[^:]*:30: Error: syntax error -- `vrshleq.s32 q0,r2'
|
||||
[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vrshlt.s32 q0,r2'
|
||||
[^:]*:33: Error: instruction missing MVE vector predication code -- `vrshl.s32 q0,r2'
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
.macro cond lastreg
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
vrshl.s32 q0, q0, \lastreg
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vrshl.i16 q0, q1, q2
|
||||
vrshl.i16 q0, r2
|
||||
vrshl.s64 q0, q1, q2
|
||||
vrshl.s64 q0, r2
|
||||
vrshl.s32 q0, sp
|
||||
vrshl.s32 q0, pc
|
||||
cond q2
|
||||
cond r2
|
||||
it eq
|
||||
vrshleq.s32 q0, q1, q2
|
||||
vrshleq.s32 q0, q1, q2
|
||||
vpst
|
||||
vrshleq.s32 q0, q1, q2
|
||||
vrshlt.s32 q0, q1, q2
|
||||
vpst
|
||||
vrshl.s32 q0, q1, q2
|
||||
it eq
|
||||
vrshleq.s32 q0, r2
|
||||
vrshleq.s32 q0, r2
|
||||
vpst
|
||||
vrshleq.s32 q0, r2
|
||||
vrshlt.s32 q0, r2
|
||||
vpst
|
||||
vrshl.s32 q0, r2
|
||||
Loading…
Reference in New Issue