[PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullb
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): Add new operand. (parse_operands): Handle new operand. (do_mve_vqdmull): New encoding function. (insns): Add entry for MVE mnemonics. * testsuite/gas/arm/mve-vqdmull-bad.d: New test. * testsuite/gas/arm/mve-vqdmull-bad.l: New test. * testsuite/gas/arm/mve-vqdmull-bad.s: New test.
This commit is contained in:
Andre Vieira
parent
42b16635dd
commit
35d1cfc200
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@ -1,3 +1,13 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum operand_parse_code): Add new operand.
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(parse_operands): Handle new operand.
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(do_mve_vqdmull): New encoding function.
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(insns): Add entry for MVE mnemonics.
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* testsuite/gas/arm/mve-vqdmull-bad.d: New test.
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* testsuite/gas/arm/mve-vqdmull-bad.l: New test.
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* testsuite/gas/arm/mve-vqdmull-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum operand_parse_code): Add new operand.
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@ -6923,6 +6923,7 @@ enum operand_parse_code
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GPR (no SP/SP) */
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OP_RMQ, /* MVE vector register. */
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OP_RMQRZ, /* MVE vector or ARM register including ZR. */
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OP_RMQRR, /* MVE vector or ARM register. */
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/* New operands for Armv8.1-M Mainline. */
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OP_LR, /* ARM LR register */
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@ -7281,6 +7282,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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po_reg_or_fail (REG_TYPE_NSDQ);
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inst.error = 0;
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break;
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case OP_RMQRR:
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po_reg_or_goto (REG_TYPE_RN, try_rmq);
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break;
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try_rmq:
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case OP_RMQ:
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po_reg_or_fail (REG_TYPE_MQ);
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break;
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@ -17282,6 +17287,35 @@ do_mve_vhcadd (void)
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inst.is_neon = 1;
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}
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static void
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do_mve_vqdmull (void)
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{
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enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
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struct neon_type_el et
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= neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
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if (et.size == 32
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&& (inst.operands[0].reg == inst.operands[1].reg
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|| (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg)))
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as_tsktsk (BAD_MVE_SRCDEST);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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if (rs == NS_QQQ)
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{
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mve_encode_qqq (et.size == 32, 64);
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inst.instruction |= 1;
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}
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else
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{
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mve_encode_qqr (64, et.size == 32, 0);
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inst.instruction |= 0x3 << 5;
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}
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}
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static void
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do_mve_vadc (void)
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{
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@ -24838,6 +24872,8 @@ static const struct asm_opcode insns[] =
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mToC("vqdmlah", ee000e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
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mToC("vqdmlash", ee001e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
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mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah),
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mToC("vqdmullt", ee301f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
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mToC("vqdmullb", ee300f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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@ -0,0 +1,5 @@
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#name: bad MVE VQDMULLT and VQDMULLB instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vqdmull-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,61 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vqdmullt.s8 q0,q1,q2'
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[^:]*:11: Error: bad type in SIMD instruction -- `vqdmullt.u8 q0,q1,q2'
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[^:]*:12: Error: bad type in SIMD instruction -- `vqdmullt.i16 q0,q1,q2'
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[^:]*:13: Error: bad type in SIMD instruction -- `vqdmullt.s64 q0,q1,q2'
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[^:]*:14: Error: bad type in SIMD instruction -- `vqdmullb.s8 q0,q1,q2'
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[^:]*:15: Error: bad type in SIMD instruction -- `vqdmullb.u8 q0,q1,q2'
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[^:]*:16: Error: bad type in SIMD instruction -- `vqdmullb.i16 q0,q1,q2'
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[^:]*:17: Error: bad type in SIMD instruction -- `vqdmullb.s64 q0,q1,q2'
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[^:]*:18: Error: bad type in SIMD instruction -- `vqdmullt.s8 q0,q1,r2'
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[^:]*:19: Error: bad type in SIMD instruction -- `vqdmullt.u8 q0,q1,r2'
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[^:]*:20: Error: bad type in SIMD instruction -- `vqdmullt.i16 q0,q1,r2'
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[^:]*:21: Error: bad type in SIMD instruction -- `vqdmullt.s64 q0,q1,r2'
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[^:]*:22: Error: bad type in SIMD instruction -- `vqdmullb.s8 q0,q1,r2'
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[^:]*:23: Error: bad type in SIMD instruction -- `vqdmullb.u8 q0,q1,r2'
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[^:]*:24: Error: bad type in SIMD instruction -- `vqdmullb.i16 q0,q1,r2'
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[^:]*:25: Error: bad type in SIMD instruction -- `vqdmullb.s64 q0,q1,r2'
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[^:]*:26: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:27: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:28: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:29: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:30: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:31: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:32: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:33: Warning: instruction is UNPREDICTABLE with PC operand
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[^:]*:34: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:41: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
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[^:]*:42: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
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[^:]*:44: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
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[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmulltt.s32 q0,q1,q2'
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[^:]*:47: Error: instruction missing MVE vector predication code -- `vqdmullt.s32 q0,q1,q2'
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[^:]*:49: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2'
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[^:]*:50: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2'
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[^:]*:52: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2'
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[^:]*:53: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmullbt.s32 q0,q1,q2'
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[^:]*:55: Error: instruction missing MVE vector predication code -- `vqdmullb.s32 q0,q1,q2'
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@ -0,0 +1,55 @@
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.macro cond op, lastreg
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s16 q0, q1, \lastreg
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.endr
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.endm
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.syntax unified
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.thumb
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vqdmullt.s8 q0, q1, q2
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vqdmullt.u8 q0, q1, q2
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vqdmullt.i16 q0, q1, q2
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vqdmullt.s64 q0, q1, q2
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vqdmullb.s8 q0, q1, q2
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vqdmullb.u8 q0, q1, q2
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vqdmullb.i16 q0, q1, q2
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vqdmullb.s64 q0, q1, q2
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vqdmullt.s8 q0, q1, r2
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vqdmullt.u8 q0, q1, r2
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vqdmullt.i16 q0, q1, r2
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vqdmullt.s64 q0, q1, r2
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vqdmullb.s8 q0, q1, r2
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vqdmullb.u8 q0, q1, r2
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vqdmullb.i16 q0, q1, r2
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vqdmullb.s64 q0, q1, r2
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vqdmullt.s32 q0, q0, q2
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vqdmullt.s32 q0, q1, q0
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vqdmullb.s32 q0, q0, q2
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vqdmullb.s32 q0, q1, q0
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vqdmullt.s32 q0, q0, r2
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vqdmullb.s32 q0, q0, r2
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vqdmullt.s16 q0, q0, sp
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vqdmullt.s16 q0, q0, pc
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vqdmullb.s16 q0, q0, sp
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vqdmullb.s16 q0, q0, pc
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cond vqdmullt, q2
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cond vqdmullb, q2
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cond vqdmullt, r2
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cond vqdmullb, r2
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it eq
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vqdmullteq.s32 q0, q1, q2
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vqdmullteq.s32 q0, q1, q2
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vpst
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vqdmullteq.s32 q0, q1, q2
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vqdmulltt.s32 q0, q1, q2
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vpst
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vqdmullt.s32 q0, q1, q2
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it eq
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vqdmullbeq.s32 q0, q1, q2
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vqdmullbeq.s32 q0, q1, q2
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vpst
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vqdmullbeq.s32 q0, q1, q2
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vqdmullbt.s32 q0, q1, q2
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vpst
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vqdmullb.s32 q0, q1, q2
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