[PATCH 28/57][Arm][GAS] Add support for MVE instructions: vqdmlah, vqrdmlah, vqdmlash, vqrdmlash, vqdmulh and vqrdmulh
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): Add new operand. (parse_operands): Handle new operand. (mve_encode_qqr): Handle new instructions. (do_neon_qdmulh): Add support for MVE variants. (do_neon_qrdmlah): Likewise. (do_mve_vqdmlah): New encoding function. (insns): Change entries and add new entries for MVE mnemonics. * testsuite/gas/arm/mve-vqdmulh-bad.d: New test. * testsuite/gas/arm/mve-vqdmulh-bad.l: New test. * testsuite/gas/arm/mve-vqdmulh-bad.s: New test.
This commit is contained in:
Andre Vieira
parent
8b8b22a426
commit
42b16635dd
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@ -1,3 +1,16 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum operand_parse_code): Add new operand.
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(parse_operands): Handle new operand.
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(mve_encode_qqr): Handle new instructions.
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(do_neon_qdmulh): Add support for MVE variants.
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(do_neon_qrdmlah): Likewise.
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(do_mve_vqdmlah): New encoding function.
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(insns): Change entries and add new entries for MVE mnemonics.
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* testsuite/gas/arm/mve-vqdmulh-bad.d: New test.
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* testsuite/gas/arm/mve-vqdmulh-bad.l: New test.
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* testsuite/gas/arm/mve-vqdmulh-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_mve_vqdmladh): New encoding function.
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@ -6954,6 +6954,9 @@ enum operand_parse_code
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OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon
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scalar, or ARM register. */
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OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
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OP_RNDQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, or ARM register. */
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OP_RNDQMQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
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register. */
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OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */
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OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
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OP_VMOV, /* Neon VMOV operands. */
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@ -7358,6 +7361,13 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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}
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break;
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case OP_RNDQMQ_RNSC_RR:
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po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc_rr);
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break;
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try_rndq_rnsc_rr:
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case OP_RNDQ_RNSC_RR:
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po_reg_or_goto (REG_TYPE_RN, try_rndq_rnsc);
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break;
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case OP_RNDQMQ_RNSC:
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po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
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break;
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@ -15993,6 +16003,15 @@ mve_encode_qqr (int size, int U, int fp)
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/* vqsub. */
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else if (((unsigned)inst.instruction) == 0x210)
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inst.instruction = 0xee001f60;
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/* vqrdmlah. */
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else if (((unsigned)inst.instruction) == 0x3000b10)
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inst.instruction = 0xee000e40;
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/* vqdmulh. */
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else if (((unsigned)inst.instruction) == 0x0000b00)
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inst.instruction = 0xee010e60;
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/* vqrdmulh. */
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else if (((unsigned)inst.instruction) == 0x1000b00)
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inst.instruction = 0xfe010e60;
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/* Set U-bit. */
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inst.instruction |= U << 28;
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@ -17181,8 +17200,12 @@ do_neon_mul (void)
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static void
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do_neon_qdmulh (void)
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{
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if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
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return;
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if (inst.operands[2].isscalar)
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{
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constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
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enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
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@ -17191,12 +17214,27 @@ do_neon_qdmulh (void)
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}
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else
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{
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enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
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enum neon_shape rs;
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struct neon_type_el et;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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{
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rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
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et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
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}
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else
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{
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rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
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et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
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}
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NEON_ENCODE (INTEGER, inst);
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/* The U bit (rounding) comes from bit mask. */
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neon_three_same (neon_quad (rs), 0, et.size);
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if (rs == NS_QQR)
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mve_encode_qqr (et.size, 0, 0);
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else
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/* The U bit (rounding) comes from bit mask. */
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neon_three_same (neon_quad (rs), 0, et.size);
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}
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}
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@ -17305,6 +17343,20 @@ do_mve_vmulh (void)
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mve_encode_qqq (et.type == NT_unsigned, et.size);
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}
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static void
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do_mve_vqdmlah (void)
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{
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enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
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struct neon_type_el et
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= neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
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}
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static void
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do_mve_vqdmladh (void)
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@ -17556,32 +17608,45 @@ do_mve_vmaxv (void)
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static void
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do_neon_qrdmlah (void)
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{
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/* Check we're on the correct architecture. */
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if (!mark_feature_used (&fpu_neon_ext_armv8))
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inst.error =
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_("instruction form not available on this architecture.");
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else if (!mark_feature_used (&fpu_neon_ext_v8_1))
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if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
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return;
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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{
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as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
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record_feature_use (&fpu_neon_ext_v8_1);
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}
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if (inst.operands[2].isscalar)
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{
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enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
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NEON_ENCODE (SCALAR, inst);
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neon_mul_mac (et, neon_quad (rs));
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/* Check we're on the correct architecture. */
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if (!mark_feature_used (&fpu_neon_ext_armv8))
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inst.error
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= _("instruction form not available on this architecture.");
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else if (!mark_feature_used (&fpu_neon_ext_v8_1))
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{
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as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
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record_feature_use (&fpu_neon_ext_v8_1);
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}
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if (inst.operands[2].isscalar)
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{
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enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
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NEON_ENCODE (SCALAR, inst);
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neon_mul_mac (et, neon_quad (rs));
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}
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else
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{
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enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
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NEON_ENCODE (INTEGER, inst);
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/* The U bit (rounding) comes from bit mask. */
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neon_three_same (neon_quad (rs), 0, et.size);
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}
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}
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else
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{
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enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
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struct neon_type_el et = neon_check_type (3, rs,
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N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
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enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
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struct neon_type_el et
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= neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
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NEON_ENCODE (INTEGER, inst);
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/* The U bit (rounding) comes from bit mask. */
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neon_three_same (neon_quad (rs), 0, et.size);
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mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
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}
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}
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@ -24068,9 +24133,7 @@ static const struct asm_opcode insns[] =
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/* VMUL takes I8 I16 I32 F32 P8. */
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nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
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/* VQD{R}MULH takes S16 S32. */
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nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
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nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
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nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
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nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
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NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
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NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
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@ -24085,7 +24148,6 @@ static const struct asm_opcode insns[] =
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NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
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NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
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/* ARM v8.1 extension. */
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nUF (vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
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nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
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nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
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nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
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@ -24773,6 +24835,9 @@ static const struct asm_opcode insns[] =
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mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
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mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
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mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
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mToC("vqdmlah", ee000e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
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mToC("vqdmlash", ee001e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
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mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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@ -24856,6 +24921,9 @@ static const struct asm_opcode insns[] =
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mnUF(vmvn, _vmvn, 2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn),
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MNUF(vqabs, 1b00700, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
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MNUF(vqneg, 1b00780, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
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mnUF(vqrdmlah, _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah),
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mnUF(vqdmulh, _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
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mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
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#undef ARM_VARIANT
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#define ARM_VARIANT & arm_ext_v8_3
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@ -0,0 +1,5 @@
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#name: bad MVE VQDMULH and VQRDMULH instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vqdmulh-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,57 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vqdmulh.s64 q0,q1,q2'
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[^:]*:11: Error: bad type in SIMD instruction -- `vqdmulh.u8 q0,q1,q2'
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[^:]*:12: Error: bad type in SIMD instruction -- `vqrdmulh.s64 q0,q1,q2'
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[^:]*:13: Error: bad type in SIMD instruction -- `vqrdmulh.u8 q0,q1,q2'
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[^:]*:14: Error: bad type in SIMD instruction -- `vqdmulh.s64 q0,q1,r2'
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[^:]*:15: Error: bad type in SIMD instruction -- `vqdmulh.u8 q0,q1,r2'
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[^:]*:16: Error: bad type in SIMD instruction -- `vqrdmulh.s64 q0,q1,r2'
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[^:]*:17: Error: bad type in SIMD instruction -- `vqrdmulh.u8 q0,q1,r2'
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[^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand
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[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Error: syntax error -- `vqdmulheq.s8 q0,q1,q2'
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[^:]*:28: Error: syntax error -- `vqdmulheq.s8 q0,q1,q2'
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[^:]*:30: Error: syntax error -- `vqdmulheq.s8 q0,q1,q2'
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[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmulht.s8 q0,q1,q2'
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[^:]*:33: Error: instruction missing MVE vector predication code -- `vqdmulh.s8 q0,q1,q2'
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[^:]*:35: Error: syntax error -- `vqrdmulheq.s8 q0,q1,q2'
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[^:]*:36: Error: syntax error -- `vqrdmulheq.s8 q0,q1,q2'
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[^:]*:38: Error: syntax error -- `vqrdmulheq.s8 q0,q1,q2'
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[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmulht.s8 q0,q1,q2'
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[^:]*:41: Error: instruction missing MVE vector predication code -- `vqrdmulh.s8 q0,q1,q2'
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[^:]*:43: Error: syntax error -- `vqdmulheq.s8 q0,q1,r2'
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[^:]*:44: Error: syntax error -- `vqdmulheq.s8 q0,q1,r2'
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[^:]*:46: Error: syntax error -- `vqdmulheq.s8 q0,q1,r2'
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[^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmulht.s8 q0,q1,r2'
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[^:]*:49: Error: instruction missing MVE vector predication code -- `vqdmulh.s8 q0,q1,r2'
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[^:]*:51: Error: syntax error -- `vqrdmulheq.s8 q0,q1,r2'
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[^:]*:52: Error: syntax error -- `vqrdmulheq.s8 q0,q1,r2'
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[^:]*:54: Error: syntax error -- `vqrdmulheq.s8 q0,q1,r2'
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[^:]*:55: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmulht.s8 q0,q1,r2'
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[^:]*:57: Error: instruction missing MVE vector predication code -- `vqrdmulh.s8 q0,q1,r2'
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@ -0,0 +1,57 @@
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.macro cond op, lastreg
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s16 q0, q1, \lastreg
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.endr
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.endm
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.syntax unified
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.thumb
|
||||
vqdmulh.s64 q0, q1, q2
|
||||
vqdmulh.u8 q0, q1, q2
|
||||
vqrdmulh.s64 q0, q1, q2
|
||||
vqrdmulh.u8 q0, q1, q2
|
||||
vqdmulh.s64 q0, q1, r2
|
||||
vqdmulh.u8 q0, q1, r2
|
||||
vqrdmulh.s64 q0, q1, r2
|
||||
vqrdmulh.u8 q0, q1, r2
|
||||
vqdmulh.s8 q0, q1, sp
|
||||
vqdmulh.s8 q0, q1, pc
|
||||
vqrdmulh.s8 q0, q1, sp
|
||||
vqrdmulh.s8 q0, q1, pc
|
||||
cond vqdmulh, q2
|
||||
cond vqrdmulh, q2
|
||||
cond vqdmulh, r2
|
||||
cond vqrdmulh, r2
|
||||
it eq
|
||||
vqdmulheq.s8 q0, q1, q2
|
||||
vqdmulheq.s8 q0, q1, q2
|
||||
vpst
|
||||
vqdmulheq.s8 q0, q1, q2
|
||||
vqdmulht.s8 q0, q1, q2
|
||||
vpst
|
||||
vqdmulh.s8 q0, q1, q2
|
||||
it eq
|
||||
vqrdmulheq.s8 q0, q1, q2
|
||||
vqrdmulheq.s8 q0, q1, q2
|
||||
vpst
|
||||
vqrdmulheq.s8 q0, q1, q2
|
||||
vqrdmulht.s8 q0, q1, q2
|
||||
vpst
|
||||
vqrdmulh.s8 q0, q1, q2
|
||||
it eq
|
||||
vqdmulheq.s8 q0, q1, r2
|
||||
vqdmulheq.s8 q0, q1, r2
|
||||
vpst
|
||||
vqdmulheq.s8 q0, q1, r2
|
||||
vqdmulht.s8 q0, q1, r2
|
||||
vpst
|
||||
vqdmulh.s8 q0, q1, r2
|
||||
it eq
|
||||
vqrdmulheq.s8 q0, q1, r2
|
||||
vqrdmulheq.s8 q0, q1, r2
|
||||
vpst
|
||||
vqrdmulheq.s8 q0, q1, r2
|
||||
vqrdmulht.s8 q0, q1, r2
|
||||
vpst
|
||||
vqrdmulh.s8 q0, q1, r2
|
||||
Loading…
Reference in New Issue