[PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, vqrdmladh, vqdmlsdh and vqrdmlsdh
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vqdmladh): New encoding function. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vqdmladh-bad.d: New test. * testsuite/gas/arm/mve-vqdmladh-bad.l: New test. * testsuite/gas/arm/mve-vqdmladh-bad.s: New test. * testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test. * testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test. * testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.
This commit is contained in:
Andre Vieira
parent
3063888ecf
commit
8b8b22a426
@ -1,3 +1,14 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_mve_vqdmladh): New encoding function.
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(insns): Add entries for MVE mnemonics.
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* testsuite/gas/arm/mve-vqdmladh-bad.d: New test.
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* testsuite/gas/arm/mve-vqdmladh-bad.l: New test.
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* testsuite/gas/arm/mve-vqdmladh-bad.s: New test.
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* testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test.
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* testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test.
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* testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_mve_vpsel): New encoding function.
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@ -17305,6 +17305,28 @@ do_mve_vmulh (void)
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mve_encode_qqq (et.type == NT_unsigned, et.size);
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}
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static void
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do_mve_vqdmladh (void)
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{
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enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
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struct neon_type_el et
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= neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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if (et.size == 32
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&& (inst.operands[0].reg == inst.operands[1].reg
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|| inst.operands[0].reg == inst.operands[2].reg))
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as_tsktsk (BAD_MVE_SRCDEST);
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mve_encode_qqq (0, et.size);
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}
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static void
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do_mve_vmull (void)
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{
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@ -24743,6 +24765,15 @@ static const struct asm_opcode insns[] =
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mToC("vpnot", fe310f4d, 0, (), mve_vpnot),
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mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel),
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mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
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mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
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mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
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mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
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mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
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mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
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mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
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mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
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5
gas/testsuite/gas/arm/mve-vqdmladh-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vqdmladh-bad.d
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@ -0,0 +1,5 @@
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#name: bad MVE VQDMLADH and VQRDMLADH instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vqdmladh-bad.l
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.*: +file format .*arm.*
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61
gas/testsuite/gas/arm/mve-vqdmladh-bad.l
Normal file
61
gas/testsuite/gas/arm/mve-vqdmladh-bad.l
Normal file
@ -0,0 +1,61 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vqdmladh.u32 q0,q1,q2'
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[^:]*:11: Error: bad type in SIMD instruction -- `vqdmladh.s64 q0,q1,q2'
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[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:14: Error: bad type in SIMD instruction -- `vqdmladhx.u32 q0,q1,q2'
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[^:]*:15: Error: bad type in SIMD instruction -- `vqdmladhx.s64 q0,q1,q2'
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[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmladh.u32 q0,q1,q2'
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[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmladh.s64 q0,q1,q2'
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[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmladhx.u32 q0,q1,q2'
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[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmladhx.s64 q0,q1,q2'
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[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:31: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
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[^:]*:32: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
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[^:]*:34: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
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[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladht.s32 q0,q1,q2'
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[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmladh.s32 q0,q1,q2'
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[^:]*:39: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
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[^:]*:40: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
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[^:]*:42: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
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[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladhxt.s32 q0,q1,q2'
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[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmladhx.s32 q0,q1,q2'
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[^:]*:47: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
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[^:]*:48: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
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[^:]*:50: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
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[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladht.s32 q0,q1,q2'
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[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmladh.s32 q0,q1,q2'
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[^:]*:55: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
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[^:]*:56: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
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[^:]*:58: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
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[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladhxt.s32 q0,q1,q2'
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[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmladhx.s32 q0,q1,q2'
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61
gas/testsuite/gas/arm/mve-vqdmladh-bad.s
Normal file
61
gas/testsuite/gas/arm/mve-vqdmladh-bad.s
Normal file
@ -0,0 +1,61 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s16 q0, q1, q2
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.endr
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.endm
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.syntax unified
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.thumb
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vqdmladh.u32 q0, q1, q2
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vqdmladh.s64 q0, q1, q2
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vqdmladh.s32 q0, q0, q2
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vqdmladh.s32 q0, q1, q0
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vqdmladhx.u32 q0, q1, q2
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vqdmladhx.s64 q0, q1, q2
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vqdmladhx.s32 q0, q0, q2
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vqdmladhx.s32 q0, q1, q0
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vqrdmladh.u32 q0, q1, q2
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vqrdmladh.s64 q0, q1, q2
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vqrdmladh.s32 q0, q0, q2
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vqrdmladh.s32 q0, q1, q0
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vqrdmladhx.u32 q0, q1, q2
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vqrdmladhx.s64 q0, q1, q2
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vqrdmladhx.s32 q0, q0, q2
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vqrdmladhx.s32 q0, q1, q0
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cond vqdmladh
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cond vqdmladhx
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cond vqrdmladh
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cond vqrdmladhx
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it eq
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vqdmladheq.s32 q0, q1, q2
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vqdmladheq.s32 q0, q1, q2
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vpst
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vqdmladheq.s32 q0, q1, q2
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vqdmladht.s32 q0, q1, q2
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vpst
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vqdmladh.s32 q0, q1, q2
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it eq
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vqdmladhxeq.s32 q0, q1, q2
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vqdmladhxeq.s32 q0, q1, q2
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vpst
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vqdmladhxeq.s32 q0, q1, q2
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vqdmladhxt.s32 q0, q1, q2
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vpst
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vqdmladhx.s32 q0, q1, q2
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it eq
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vqrdmladheq.s32 q0, q1, q2
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vqrdmladheq.s32 q0, q1, q2
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vpst
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vqrdmladheq.s32 q0, q1, q2
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vqrdmladht.s32 q0, q1, q2
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vpst
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vqrdmladh.s32 q0, q1, q2
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it eq
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vqrdmladhxeq.s32 q0, q1, q2
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vqrdmladhxeq.s32 q0, q1, q2
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vpst
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vqrdmladhxeq.s32 q0, q1, q2
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vqrdmladhxt.s32 q0, q1, q2
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vpst
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vqrdmladhx.s32 q0, q1, q2
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5
gas/testsuite/gas/arm/mve-vqdmlsdh-bad.d
Normal file
5
gas/testsuite/gas/arm/mve-vqdmlsdh-bad.d
Normal file
@ -0,0 +1,5 @@
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#name: bad MVE VQDMLSDH and VQRDMLSDH instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vqdmlsdh-bad.l
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.*: +file format .*arm.*
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61
gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l
Normal file
61
gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l
Normal file
@ -0,0 +1,61 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vqdmlsdh.u32 q0,q1,q2'
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[^:]*:11: Error: bad type in SIMD instruction -- `vqdmlsdh.s64 q0,q1,q2'
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[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:14: Error: bad type in SIMD instruction -- `vqdmlsdhx.u32 q0,q1,q2'
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[^:]*:15: Error: bad type in SIMD instruction -- `vqdmlsdhx.s64 q0,q1,q2'
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[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmlsdh.u32 q0,q1,q2'
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[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmlsdh.s64 q0,q1,q2'
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[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmlsdhx.u32 q0,q1,q2'
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[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmlsdhx.s64 q0,q1,q2'
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[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:31: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
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[^:]*:32: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
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[^:]*:34: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
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[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdht.s32 q0,q1,q2'
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[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmlsdh.s32 q0,q1,q2'
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[^:]*:39: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
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[^:]*:40: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
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[^:]*:42: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
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[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdhxt.s32 q0,q1,q2'
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[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmlsdhx.s32 q0,q1,q2'
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[^:]*:47: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
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[^:]*:48: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
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[^:]*:50: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
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[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdht.s32 q0,q1,q2'
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[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmlsdh.s32 q0,q1,q2'
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[^:]*:55: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
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[^:]*:56: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
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[^:]*:58: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
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[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdhxt.s32 q0,q1,q2'
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[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmlsdhx.s32 q0,q1,q2'
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61
gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s
Normal file
61
gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s
Normal file
@ -0,0 +1,61 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().s16 q0, q1, q2
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.endr
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.endm
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.syntax unified
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.thumb
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vqdmlsdh.u32 q0, q1, q2
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vqdmlsdh.s64 q0, q1, q2
|
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vqdmlsdh.s32 q0, q0, q2
|
||||
vqdmlsdh.s32 q0, q1, q0
|
||||
vqdmlsdhx.u32 q0, q1, q2
|
||||
vqdmlsdhx.s64 q0, q1, q2
|
||||
vqdmlsdhx.s32 q0, q0, q2
|
||||
vqdmlsdhx.s32 q0, q1, q0
|
||||
vqrdmlsdh.u32 q0, q1, q2
|
||||
vqrdmlsdh.s64 q0, q1, q2
|
||||
vqrdmlsdh.s32 q0, q0, q2
|
||||
vqrdmlsdh.s32 q0, q1, q0
|
||||
vqrdmlsdhx.u32 q0, q1, q2
|
||||
vqrdmlsdhx.s64 q0, q1, q2
|
||||
vqrdmlsdhx.s32 q0, q0, q2
|
||||
vqrdmlsdhx.s32 q0, q1, q0
|
||||
cond vqdmlsdh
|
||||
cond vqdmlsdhx
|
||||
cond vqrdmlsdh
|
||||
cond vqrdmlsdhx
|
||||
it eq
|
||||
vqdmlsdheq.s32 q0, q1, q2
|
||||
vqdmlsdheq.s32 q0, q1, q2
|
||||
vpst
|
||||
vqdmlsdheq.s32 q0, q1, q2
|
||||
vqdmlsdht.s32 q0, q1, q2
|
||||
vpst
|
||||
vqdmlsdh.s32 q0, q1, q2
|
||||
it eq
|
||||
vqdmlsdhxeq.s32 q0, q1, q2
|
||||
vqdmlsdhxeq.s32 q0, q1, q2
|
||||
vpst
|
||||
vqdmlsdhxeq.s32 q0, q1, q2
|
||||
vqdmlsdhxt.s32 q0, q1, q2
|
||||
vpst
|
||||
vqdmlsdhx.s32 q0, q1, q2
|
||||
it eq
|
||||
vqrdmlsdheq.s32 q0, q1, q2
|
||||
vqrdmlsdheq.s32 q0, q1, q2
|
||||
vpst
|
||||
vqrdmlsdheq.s32 q0, q1, q2
|
||||
vqrdmlsdht.s32 q0, q1, q2
|
||||
vpst
|
||||
vqrdmlsdh.s32 q0, q1, q2
|
||||
it eq
|
||||
vqrdmlsdhxeq.s32 q0, q1, q2
|
||||
vqrdmlsdhxeq.s32 q0, q1, q2
|
||||
vpst
|
||||
vqrdmlsdhxeq.s32 q0, q1, q2
|
||||
vqrdmlsdhxt.s32 q0, q1, q2
|
||||
vpst
|
||||
vqrdmlsdhx.s32 q0, q1, q2
|
||||
Loading…
x
Reference in New Issue
Block a user