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[PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, vqrdmladh, vqdmlsdh and vqrdmlsdh 

gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (do_mve_vqdmladh): New encoding function.
	(insns): Add entries for MVE mnemonics.
	* testsuite/gas/arm/mve-vqdmladh-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmladh-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmladh-bad.s: New test.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.
This commit is contained in:
Andre Vieira 2019-05-16 11:59:36 +01:00
parent 3063888ecf
commit 8b8b22a426
8 changed files with 296 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
gas/ChangeLog
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@ -1,3 +1,14 @@
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vqdmladh): New encoding function.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vqdmladh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmladh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmladh-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vpsel): New encoding function.

31
gas/config/tc-arm.c
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@ -17305,6 +17305,28 @@ do_mve_vmulh (void)
mve_encode_qqq (et.type == NT_unsigned, et.size);
}
static void
do_mve_vqdmladh (void)
{
enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
struct neon_type_el et
= neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
if (inst.cond > COND_ALWAYS)
inst.pred_insn_type = INSIDE_VPT_INSN;
else
inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
if (et.size == 32
&& (inst.operands[0].reg == inst.operands[1].reg
|| inst.operands[0].reg == inst.operands[2].reg))
as_tsktsk (BAD_MVE_SRCDEST);
mve_encode_qqq (0, et.size);
}
static void
do_mve_vmull (void)
{
@ -24743,6 +24765,15 @@ static const struct asm_opcode insns[] =
mToC("vpnot", fe310f4d, 0, (), mve_vpnot),
mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel),
mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
#undef THUMB_VARIANT
#define THUMB_VARIANT & mve_fp_ext
mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),

5
gas/testsuite/gas/arm/mve-vqdmladh-bad.d Normal file
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@ -0,0 +1,5 @@
#name: bad MVE VQDMLADH and VQRDMLADH instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vqdmladh-bad.l
.*: +file format .*arm.*

61
gas/testsuite/gas/arm/mve-vqdmladh-bad.l Normal file
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@ -0,0 +1,61 @@
[^:]*: Assembler messages:
[^:]*:10: Error: bad type in SIMD instruction -- `vqdmladh.u32 q0,q1,q2'
[^:]*:11: Error: bad type in SIMD instruction -- `vqdmladh.s64 q0,q1,q2'
[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:14: Error: bad type in SIMD instruction -- `vqdmladhx.u32 q0,q1,q2'
[^:]*:15: Error: bad type in SIMD instruction -- `vqdmladhx.s64 q0,q1,q2'
[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmladh.u32 q0,q1,q2'
[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmladh.s64 q0,q1,q2'
[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmladhx.u32 q0,q1,q2'
[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmladhx.s64 q0,q1,q2'
[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:31: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
[^:]*:32: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
[^:]*:34: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladht.s32 q0,q1,q2'
[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmladh.s32 q0,q1,q2'
[^:]*:39: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
[^:]*:40: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
[^:]*:42: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladhxt.s32 q0,q1,q2'
[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmladhx.s32 q0,q1,q2'
[^:]*:47: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
[^:]*:48: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
[^:]*:50: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladht.s32 q0,q1,q2'
[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmladh.s32 q0,q1,q2'
[^:]*:55: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
[^:]*:56: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
[^:]*:58: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladhxt.s32 q0,q1,q2'
[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmladhx.s32 q0,q1,q2'

61
gas/testsuite/gas/arm/mve-vqdmladh-bad.s Normal file
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@ -0,0 +1,61 @@
.macro cond op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 q0, q1, q2
.endr
.endm
.syntax unified
.thumb
vqdmladh.u32 q0, q1, q2
vqdmladh.s64 q0, q1, q2
vqdmladh.s32 q0, q0, q2
vqdmladh.s32 q0, q1, q0
vqdmladhx.u32 q0, q1, q2
vqdmladhx.s64 q0, q1, q2
vqdmladhx.s32 q0, q0, q2
vqdmladhx.s32 q0, q1, q0
vqrdmladh.u32 q0, q1, q2
vqrdmladh.s64 q0, q1, q2
vqrdmladh.s32 q0, q0, q2
vqrdmladh.s32 q0, q1, q0
vqrdmladhx.u32 q0, q1, q2
vqrdmladhx.s64 q0, q1, q2
vqrdmladhx.s32 q0, q0, q2
vqrdmladhx.s32 q0, q1, q0
cond vqdmladh
cond vqdmladhx
cond vqrdmladh
cond vqrdmladhx
it eq
vqdmladheq.s32 q0, q1, q2
vqdmladheq.s32 q0, q1, q2
vpst
vqdmladheq.s32 q0, q1, q2
vqdmladht.s32 q0, q1, q2
vpst
vqdmladh.s32 q0, q1, q2
it eq
vqdmladhxeq.s32 q0, q1, q2
vqdmladhxeq.s32 q0, q1, q2
vpst
vqdmladhxeq.s32 q0, q1, q2
vqdmladhxt.s32 q0, q1, q2
vpst
vqdmladhx.s32 q0, q1, q2
it eq
vqrdmladheq.s32 q0, q1, q2
vqrdmladheq.s32 q0, q1, q2
vpst
vqrdmladheq.s32 q0, q1, q2
vqrdmladht.s32 q0, q1, q2
vpst
vqrdmladh.s32 q0, q1, q2
it eq
vqrdmladhxeq.s32 q0, q1, q2
vqrdmladhxeq.s32 q0, q1, q2
vpst
vqrdmladhxeq.s32 q0, q1, q2
vqrdmladhxt.s32 q0, q1, q2
vpst
vqrdmladhx.s32 q0, q1, q2

5
gas/testsuite/gas/arm/mve-vqdmlsdh-bad.d Normal file
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@ -0,0 +1,5 @@
#name: bad MVE VQDMLSDH and VQRDMLSDH instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vqdmlsdh-bad.l
.*: +file format .*arm.*

61
gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l Normal file
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@ -0,0 +1,61 @@
[^:]*: Assembler messages:
[^:]*:10: Error: bad type in SIMD instruction -- `vqdmlsdh.u32 q0,q1,q2'
[^:]*:11: Error: bad type in SIMD instruction -- `vqdmlsdh.s64 q0,q1,q2'
[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:14: Error: bad type in SIMD instruction -- `vqdmlsdhx.u32 q0,q1,q2'
[^:]*:15: Error: bad type in SIMD instruction -- `vqdmlsdhx.s64 q0,q1,q2'
[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmlsdh.u32 q0,q1,q2'
[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmlsdh.s64 q0,q1,q2'
[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmlsdhx.u32 q0,q1,q2'
[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmlsdhx.s64 q0,q1,q2'
[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:31: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
[^:]*:32: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
[^:]*:34: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdht.s32 q0,q1,q2'
[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmlsdh.s32 q0,q1,q2'
[^:]*:39: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
[^:]*:40: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
[^:]*:42: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdhxt.s32 q0,q1,q2'
[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmlsdhx.s32 q0,q1,q2'
[^:]*:47: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
[^:]*:48: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
[^:]*:50: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdht.s32 q0,q1,q2'
[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmlsdh.s32 q0,q1,q2'
[^:]*:55: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
[^:]*:56: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
[^:]*:58: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdhxt.s32 q0,q1,q2'
[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmlsdhx.s32 q0,q1,q2'

61
gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s Normal file
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@ -0,0 +1,61 @@
.macro cond op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 q0, q1, q2
.endr
.endm
.syntax unified
.thumb
vqdmlsdh.u32 q0, q1, q2
vqdmlsdh.s64 q0, q1, q2
vqdmlsdh.s32 q0, q0, q2
vqdmlsdh.s32 q0, q1, q0
vqdmlsdhx.u32 q0, q1, q2
vqdmlsdhx.s64 q0, q1, q2
vqdmlsdhx.s32 q0, q0, q2
vqdmlsdhx.s32 q0, q1, q0
vqrdmlsdh.u32 q0, q1, q2
vqrdmlsdh.s64 q0, q1, q2
vqrdmlsdh.s32 q0, q0, q2
vqrdmlsdh.s32 q0, q1, q0
vqrdmlsdhx.u32 q0, q1, q2
vqrdmlsdhx.s64 q0, q1, q2
vqrdmlsdhx.s32 q0, q0, q2
vqrdmlsdhx.s32 q0, q1, q0
cond vqdmlsdh
cond vqdmlsdhx
cond vqrdmlsdh
cond vqrdmlsdhx
it eq
vqdmlsdheq.s32 q0, q1, q2
vqdmlsdheq.s32 q0, q1, q2
vpst
vqdmlsdheq.s32 q0, q1, q2
vqdmlsdht.s32 q0, q1, q2
vpst
vqdmlsdh.s32 q0, q1, q2
it eq
vqdmlsdhxeq.s32 q0, q1, q2
vqdmlsdhxeq.s32 q0, q1, q2
vpst
vqdmlsdhxeq.s32 q0, q1, q2
vqdmlsdhxt.s32 q0, q1, q2
vpst
vqdmlsdhx.s32 q0, q1, q2
it eq
vqrdmlsdheq.s32 q0, q1, q2
vqrdmlsdheq.s32 q0, q1, q2
vpst
vqrdmlsdheq.s32 q0, q1, q2
vqrdmlsdht.s32 q0, q1, q2
vpst
vqrdmlsdh.s32 q0, q1, q2
it eq
vqrdmlsdhxeq.s32 q0, q1, q2
vqrdmlsdhxeq.s32 q0, q1, q2
vpst
vqrdmlsdhxeq.s32 q0, q1, q2
vqrdmlsdhxt.s32 q0, q1, q2
vpst
vqrdmlsdhx.s32 q0, q1, q2