[PATCH 26/57][Arm][GAS] Add support for MVE instructions: vpnot and vpsel

gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (do_mve_vpsel): New encoding function.
	(do_mve_vpnot): Likewise.
	(insns): Add entries for MVE mnemonics.
	* testsuite/gas/arm/mve-vpnot-bad.d: New test.
	* testsuite/gas/arm/mve-vpnot-bad.l: New test.
	* testsuite/gas/arm/mve-vpnot-bad.s: New test.
	* testsuite/gas/arm/mve-vpsel-bad.d: New test.
	* testsuite/gas/arm/mve-vpsel-bad.l: New test.
	* testsuite/gas/arm/mve-vpsel-bad.s: New test.
This commit is contained in:
Andre Vieira 2019-05-16 11:57:44 +01:00
parent 1a186d296c
commit 3063888ecf
8 changed files with 113 additions and 0 deletions

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@ -1,3 +1,15 @@
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vpsel): New encoding function.
(do_mve_vpnot): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vpnot-bad.d: New test.
* testsuite/gas/arm/mve-vpnot-bad.l: New test.
* testsuite/gas/arm/mve-vpnot-bad.s: New test.
* testsuite/gas/arm/mve-vpsel-bad.d: New test.
* testsuite/gas/arm/mve-vpsel-bad.l: New test.
* testsuite/gas/arm/mve-vpsel-bad.s: New test.
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_mvn): Change to accept MVE variants.

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@ -15731,6 +15731,34 @@ do_mve_vmlas (void)
inst.is_neon = 1;
}
static void
do_mve_vpsel (void)
{
neon_select_shape (NS_QQQ, NS_NULL);
if (inst.cond > COND_ALWAYS)
inst.pred_insn_type = INSIDE_VPT_INSN;
else
inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= HI1 (inst.operands[1].reg) << 7;
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
inst.instruction |= LOW4 (inst.operands[2].reg);
inst.is_neon = 1;
}
static void
do_mve_vpnot (void)
{
if (inst.cond > COND_ALWAYS)
inst.pred_insn_type = INSIDE_VPT_INSN;
else
inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
}
static void
do_mve_vmaxnma_vminnma (void)
{
@ -24712,6 +24740,8 @@ static const struct asm_opcode insns[] =
mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas),
mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
mToC("vpnot", fe310f4d, 0, (), mve_vpnot),
mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel),
#undef THUMB_VARIANT
#define THUMB_VARIANT & mve_fp_ext

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@ -0,0 +1,5 @@
#name: bad MVE VPNOT instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vpnot-bad.l
.*: +file format .*arm.*

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@ -0,0 +1,12 @@
[^:]*: Assembler messages:
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Error: syntax error -- `vpnoteq'
[^:]*:13: Error: syntax error -- `vpnoteq'
[^:]*:15: Error: syntax error -- `vpnoteq'
[^:]*:16: Error: vector predicated instruction should be in VPT/VPST block -- `vpnott'
[^:]*:18: Error: instruction missing MVE vector predication code -- `vpnot'

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@ -0,0 +1,18 @@
.macro cond
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vpnot
.endr
.endm
.syntax unified
.thumb
cond
it eq
vpnoteq
vpnoteq
vpst
vpnoteq
vpnott
vpst
vpnot

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@ -0,0 +1,5 @@
#name: bad MVE VPSEL instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vpsel-bad.l
.*: +file format .*arm.*

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@ -0,0 +1,12 @@
[^:]*: Assembler messages:
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Error: syntax error -- `vpseleq.i16 q0,q1,q2'
[^:]*:13: Error: syntax error -- `vpseleq.i16 q0,q1,q2'
[^:]*:15: Error: syntax error -- `vpseleq.i16 q0,q1,q2'
[^:]*:16: Error: vector predicated instruction should be in VPT/VPST block -- `vpselt.i16 q0,q1,q2'
[^:]*:18: Error: instruction missing MVE vector predication code -- `vpsel.i16 q0,q1,q2'

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@ -0,0 +1,19 @@
.macro cond
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vpsel.i16 q0, q1, q2
.endr
.endm
.syntax unified
.thumb
cond
it eq
vpseleq.i16 q0, q1, q2
vpseleq.i16 q0, q1, q2
vpst
vpseleq.i16 q0, q1, q2
vpselt.i16 q0, q1, q2
vpst
vpsel.i16 q0, q1, q2