[PATCH 12/57][Arm][GAS] Add support for MVE instructions: vaddlv and vaddv
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vaddlv, M_MNEM_vaddlva, M_MNEM_vaddv, M_MNEM_vaddva): New instruction encodings. (mve_encode_rq): New encoding helper function. (do_mve_vaddlv): New encoding function. (do_mve_vaddv): New encoding function. * testsuite/gas/arm/mve-vaddlv-bad.d: New test. * testsuite/gas/arm/mve-vaddlv-bad.l: New test. * testsuite/gas/arm/mve-vaddlv-bad.s: New test. * testsuite/gas/arm/mve-vaddv-bad.d: New test. * testsuite/gas/arm/mve-vaddv-bad.l: New test. * testsuite/gas/arm/mve-vaddv-bad.s: New test.
This commit is contained in:
Andre Vieira
parent
c2dafc2a05
commit
26c1e78092
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@ -1,3 +1,17 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (M_MNEM_vaddlv, M_MNEM_vaddlva, M_MNEM_vaddv,
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M_MNEM_vaddva): New instruction encodings.
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(mve_encode_rq): New encoding helper function.
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(do_mve_vaddlv): New encoding function.
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(do_mve_vaddv): New encoding function.
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* testsuite/gas/arm/mve-vaddlv-bad.d: New test.
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* testsuite/gas/arm/mve-vaddlv-bad.l: New test.
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* testsuite/gas/arm/mve-vaddlv-bad.s: New test.
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* testsuite/gas/arm/mve-vaddv-bad.d: New test.
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* testsuite/gas/arm/mve-vaddv-bad.l: New test.
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* testsuite/gas/arm/mve-vaddv-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (M_MNEM_vadc, M_MNEM_vadci, M_MNEM_vbrsr):
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@ -14139,6 +14139,10 @@ do_t_loloop (void)
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#define M_MNEM_vadc 0xee300f00
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#define M_MNEM_vadci 0xee301f00
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#define M_MNEM_vbrsr 0xfe011e60
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#define M_MNEM_vaddlv 0xee890f00
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#define M_MNEM_vaddlva 0xee890f20
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#define M_MNEM_vaddv 0xeef10f00
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#define M_MNEM_vaddva 0xeef10f20
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/* Neon instruction encoder helpers. */
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@ -14315,6 +14319,8 @@ NEON_ENC_TAB
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X(3, (D, D, S), DOUBLE), \
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X(3, (Q, Q, S), QUAD), \
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X(3, (Q, Q, R), QUAD), \
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X(3, (R, R, Q), QUAD), \
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X(2, (R, Q), QUAD), \
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X(2, (D, D), DOUBLE), \
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X(2, (Q, Q), QUAD), \
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X(2, (D, S), DOUBLE), \
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@ -15763,6 +15769,15 @@ mve_encode_qqq (int ubit, int size)
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inst.is_neon = 1;
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}
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static void
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mve_encode_rq (unsigned bit28, unsigned size)
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{
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inst.instruction |= bit28 << 28;
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inst.instruction |= neon_logbits (size) << 18;
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inst.instruction |= inst.operands[0].reg << 12;
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inst.instruction |= LOW4 (inst.operands[1].reg);
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inst.is_neon = 1;
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}
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/* Encode insns with bit pattern:
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@ -16486,6 +16501,30 @@ do_mve_vst_vld (void)
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inst.is_neon = 1;
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}
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static void
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do_mve_vaddlv (void)
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{
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enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL);
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struct neon_type_el et
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= neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY);
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if (et.type == NT_invtype)
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first_error (BAD_EL_TYPE);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
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inst.instruction |= (et.type == NT_unsigned) << 28;
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inst.instruction |= inst.operands[1].reg << 19;
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inst.instruction |= inst.operands[0].reg << 12;
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inst.instruction |= inst.operands[2].reg;
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inst.is_neon = 1;
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}
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static void
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do_neon_dyadic_if_su (void)
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{
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@ -16761,6 +16800,26 @@ do_neon_qdmulh (void)
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}
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}
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static void
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do_mve_vaddv (void)
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{
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enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
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struct neon_type_el et
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= neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
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if (et.type == NT_invtype)
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first_error (BAD_EL_TYPE);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
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mve_encode_rq (et.type == NT_unsigned, et.size);
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}
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static void
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do_mve_vadc (void)
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{
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@ -23999,6 +24058,10 @@ static const struct asm_opcode insns[] =
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mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn),
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mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn),
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mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr),
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mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv),
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mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
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mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
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mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_vfp_ext_v1
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@ -0,0 +1,5 @@
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#name: Bad MVE VADDLV instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vaddlv-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,42 @@
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[^:]*: Assembler messages:
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Error: bad type in SIMD instruction -- `vaddlv.i32 r0,r1,q0'
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[^:]*:14: Error: bad type in SIMD instruction -- `vaddlv.f32 r0,r1,q0'
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[^:]*:15: Error: bad type in SIMD instruction -- `vaddlv.s8 r0,r1,q0'
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[^:]*:16: Error: bad type in SIMD instruction -- `vaddlv.s16 r0,r1,q0'
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[^:]*:17: Error: bad type in SIMD instruction -- `vaddlv.s64 r0,r1,q0'
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[^:]*:18: Error: bad type in SIMD instruction -- `vaddlv.u8 r0,r1,q0'
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[^:]*:19: Error: bad type in SIMD instruction -- `vaddlv.u16 r0,r1,q0'
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[^:]*:20: Error: bad type in SIMD instruction -- `vaddlv.u64 r0,r1,q0'
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[^:]*:21: Error: bad type in SIMD instruction -- `vaddlva.i32 r0,r1,q0'
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[^:]*:22: Error: bad type in SIMD instruction -- `vaddlva.f32 r0,r1,q0'
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[^:]*:23: Error: bad type in SIMD instruction -- `vaddlva.s8 r0,r1,q0'
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[^:]*:24: Error: bad type in SIMD instruction -- `vaddlva.s16 r0,r1,q0'
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[^:]*:25: Error: bad type in SIMD instruction -- `vaddlva.s64 r0,r1,q0'
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[^:]*:26: Error: bad type in SIMD instruction -- `vaddlva.u8 r0,r1,q0'
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[^:]*:27: Error: bad type in SIMD instruction -- `vaddlva.u16 r0,r1,q0'
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[^:]*:28: Error: bad type in SIMD instruction -- `vaddlva.u64 r0,r1,q0'
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[^:]*:29: Error: Odd register not allowed here -- `vaddlv.s32 r1,r3,q0'
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[^:]*:30: Error: Even register not allowed here -- `vaddlva.s32 r0,r2,q0'
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[^:]*:31: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:33: Error: syntax error -- `vaddlveq.s32 r0,r1,q0'
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[^:]*:34: Error: syntax error -- `vaddlveq.s32 r0,r1,q0'
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[^:]*:36: Error: syntax error -- `vaddlveq.s32 r0,r1,q0'
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[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vaddlvt.s32 r0,r1,q0'
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[^:]*:39: Error: instruction missing MVE vector predication code -- `vaddlv.s32 r0,r1,q0'
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[^:]*:41: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0'
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[^:]*:42: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0'
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[^:]*:44: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0'
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[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vaddlvat.s32 r0,r1,q0'
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[^:]*:47: Error: instruction missing MVE vector predication code -- `vaddlva.s32 r0,r1,q0'
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@ -0,0 +1,47 @@
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.macro cond
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.irp cond, eq, ne, gt, ge, lt, le
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.irp mnem, vaddlv.s32, vaddlva.u32
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it \cond
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\mnem r0, r1, q0
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.endr
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.endr
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.endm
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.syntax unified
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.thumb
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cond
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vaddlv.i32 r0, r1, q0
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vaddlv.f32 r0, r1, q0
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vaddlv.s8 r0, r1, q0
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vaddlv.s16 r0, r1, q0
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vaddlv.s64 r0, r1, q0
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vaddlv.u8 r0, r1, q0
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vaddlv.u16 r0, r1, q0
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vaddlv.u64 r0, r1, q0
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vaddlva.i32 r0, r1, q0
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vaddlva.f32 r0, r1, q0
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vaddlva.s8 r0, r1, q0
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vaddlva.s16 r0, r1, q0
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vaddlva.s64 r0, r1, q0
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vaddlva.u8 r0, r1, q0
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vaddlva.u16 r0, r1, q0
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vaddlva.u64 r0, r1, q0
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vaddlv.s32 r1, r3, q0
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vaddlva.s32 r0, r2, q0
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vaddlv.s32 r0, sp, q0
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it eq
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vaddlveq.s32 r0, r1, q0
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vaddlveq.s32 r0, r1, q0
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vpst
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vaddlveq.s32 r0, r1, q0
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vaddlvt.s32 r0, r1, q0
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vpst
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vaddlv.s32 r0, r1, q0
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it eq
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vaddlvaeq.s32 r0, r1, q0
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vaddlvaeq.s32 r0, r1, q0
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vpst
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vaddlvaeq.s32 r0, r1, q0
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vaddlvat.s32 r0, r1, q0
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vpst
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vaddlva.s32 r0, r1, q0
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@ -0,0 +1,5 @@
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#name: bad MVE VADDV instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vaddv-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,32 @@
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[^:]*: Assembler messages:
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:13: Error: bad type in SIMD instruction -- `vaddv.i32 r0,q0'
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[^:]*:14: Error: bad type in SIMD instruction -- `vaddv.f32 r0,q0'
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[^:]*:15: Error: bad type in SIMD instruction -- `vaddv.s64 r0,q0'
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[^:]*:16: Error: bad type in SIMD instruction -- `vaddv.u64 r0,q0'
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[^:]*:17: Error: bad type in SIMD instruction -- `vaddva.i32 r0,q0'
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[^:]*:18: Error: bad type in SIMD instruction -- `vaddva.f32 r0,q0'
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[^:]*:19: Error: bad type in SIMD instruction -- `vaddva.s64 r0,q0'
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[^:]*:20: Error: bad type in SIMD instruction -- `vaddva.u64 r0,q0'
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[^:]*:21: Error: Odd register not allowed here -- `vaddv.s32 r1,q0'
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[^:]*:23: Error: syntax error -- `vaddveq.s32 r0,q0'
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[^:]*:24: Error: syntax error -- `vaddveq.s32 r0,q0'
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[^:]*:26: Error: syntax error -- `vaddveq.s32 r0,q0'
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[^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vaddvt.s32 r0,q0'
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[^:]*:29: Error: instruction missing MVE vector predication code -- `vaddv.s32 r0,q0'
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[^:]*:31: Error: syntax error -- `vaddvaeq.s32 r0,q0'
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[^:]*:32: Error: syntax error -- `vaddvaeq.s32 r0,q0'
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[^:]*:34: Error: syntax error -- `vaddvaeq.s32 r0,q0'
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[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vaddvat.s32 r0,q0'
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[^:]*:37: Error: instruction missing MVE vector predication code -- `vaddva.s32 r0,q0'
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@ -0,0 +1,37 @@
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.macro cond
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.irp cond, eq, ne, gt, ge, lt, le
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.irp mnem, vaddv.s32, vaddva.u32
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it \cond
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\mnem r0, q0
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.endr
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.endr
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.endm
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.syntax unified
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.thumb
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cond
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vaddv.i32 r0, q0
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vaddv.f32 r0, q0
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vaddv.s64 r0, q0
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vaddv.u64 r0, q0
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vaddva.i32 r0, q0
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vaddva.f32 r0, q0
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vaddva.s64 r0, q0
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vaddva.u64 r0, q0
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vaddv.s32 r1, q0
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it eq
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vaddveq.s32 r0, q0
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vaddveq.s32 r0, q0
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vpst
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vaddveq.s32 r0, q0
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vaddvt.s32 r0, q0
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vpst
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vaddv.s32 r0, q0
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it eq
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vaddvaeq.s32 r0, q0
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vaddvaeq.s32 r0, q0
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vpst
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vaddvaeq.s32 r0, q0
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vaddvat.s32 r0, q0
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vpst
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vaddva.s32 r0, q0
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