[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.
New operand describes a shift-left immediate encoded in bits 22:20-19:18-16 where UInt(bits) - esize == shift. This operand is useful for instructions like sshllb. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHLIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 operand.
This commit is contained in:
Matthew Malcomson
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@ -1,3 +1,8 @@
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
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operand.
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
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@ -5786,6 +5786,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SVE_LIMM_MOV:
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case AARCH64_OPND_SVE_SHLIMM_PRED:
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case AARCH64_OPND_SVE_SHLIMM_UNPRED:
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case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
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case AARCH64_OPND_SVE_SHRIMM_PRED:
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case AARCH64_OPND_SVE_SHRIMM_UNPRED:
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case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
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@ -1,3 +1,8 @@
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
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operand.
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
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@ -392,6 +392,7 @@ enum aarch64_opnd
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AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
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AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
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AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
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AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */
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AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
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AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
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AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */
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@ -1,3 +1,14 @@
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
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for SVE_SHLIMM_UNPRED_22.
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(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
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* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
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operand.
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2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
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* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
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@ -638,7 +638,6 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 169:
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case 170:
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case 171:
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case 185:
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case 186:
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case 187:
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case 188:
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@ -647,8 +646,9 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 191:
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case 192:
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case 193:
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case 199:
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case 202:
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case 194:
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case 200:
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case 203:
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return aarch64_ins_regno (self, info, code, inst, errors);
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case 14:
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return aarch64_ins_reg_extended (self, info, code, inst, errors);
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@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 32:
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case 33:
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case 34:
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case 205:
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case 206:
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return aarch64_ins_reglane (self, info, code, inst, errors);
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case 35:
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return aarch64_ins_reglist (self, info, code, inst, errors);
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@ -696,7 +696,6 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 82:
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case 159:
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case 161:
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case 177:
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case 178:
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case 179:
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case 180:
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@ -704,7 +703,8 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 182:
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case 183:
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case 184:
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case 204:
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case 185:
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case 205:
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return aarch64_ins_imm (self, info, code, inst, errors);
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case 43:
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case 44:
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@ -842,21 +842,22 @@ aarch64_insert_operand (const aarch64_operand *self,
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return aarch64_ins_sve_scale (self, info, code, inst, errors);
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case 172:
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case 173:
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return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
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case 174:
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return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
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case 175:
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case 176:
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case 177:
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return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
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case 194:
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case 195:
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case 196:
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case 197:
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case 198:
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case 199:
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return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
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case 200:
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return aarch64_ins_sve_index (self, info, code, inst, errors);
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case 201:
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case 203:
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return aarch64_ins_sve_index (self, info, code, inst, errors);
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case 202:
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case 204:
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return aarch64_ins_sve_reglist (self, info, code, inst, errors);
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default: assert (0); abort ();
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}
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@ -20069,7 +20069,6 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 169:
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case 170:
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case 171:
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case 185:
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case 186:
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case 187:
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case 188:
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@ -20078,8 +20077,9 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 191:
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case 192:
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case 193:
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case 199:
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case 202:
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case 194:
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case 200:
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case 203:
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return aarch64_ext_regno (self, info, code, inst, errors);
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case 9:
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return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
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@ -20095,7 +20095,7 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 32:
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case 33:
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case 34:
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case 205:
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case 206:
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return aarch64_ext_reglane (self, info, code, inst, errors);
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case 35:
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return aarch64_ext_reglist (self, info, code, inst, errors);
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@ -20132,7 +20132,6 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 82:
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case 159:
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case 161:
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case 177:
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case 178:
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case 179:
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case 180:
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@ -20140,7 +20139,8 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 182:
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case 183:
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case 184:
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case 204:
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case 185:
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case 205:
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return aarch64_ext_imm (self, info, code, inst, errors);
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case 43:
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case 44:
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@ -20280,21 +20280,22 @@ aarch64_extract_operand (const aarch64_operand *self,
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return aarch64_ext_sve_scale (self, info, code, inst, errors);
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case 172:
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case 173:
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return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
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case 174:
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return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
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case 175:
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case 176:
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case 177:
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return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
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case 194:
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case 195:
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case 196:
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case 197:
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case 198:
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case 199:
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return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
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case 200:
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return aarch64_ext_sve_index (self, info, code, inst, errors);
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case 201:
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case 203:
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return aarch64_ext_sve_index (self, info, code, inst, errors);
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case 202:
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case 204:
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return aarch64_ext_sve_reglist (self, info, code, inst, errors);
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default: assert (0); abort ();
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}
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@ -198,6 +198,7 @@ const struct aarch64_operand aarch64_operands[] =
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{AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-left immediate operand"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"},
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{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-right immediate operand"},
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@ -2531,6 +2531,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
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case AARCH64_OPND_SVE_SHLIMM_PRED:
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case AARCH64_OPND_SVE_SHLIMM_UNPRED:
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case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
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size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
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if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
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{
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@ -3358,6 +3359,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
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case AARCH64_OPND_SIMM5:
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case AARCH64_OPND_SVE_SHLIMM_PRED:
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case AARCH64_OPND_SVE_SHLIMM_UNPRED:
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case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
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case AARCH64_OPND_SVE_SHRIMM_PRED:
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case AARCH64_OPND_SVE_SHRIMM_UNPRED:
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case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
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@ -4923,6 +4923,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
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F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \
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Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \
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F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand") \
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Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED_22", 0, \
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F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3), \
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"a shift-left immediate operand") \
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Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB, \
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F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand") \
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Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB, \
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