[BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch adds all the data cache instructions that are part of this extension: - DC IGVAC, Xt - DC IGSW, Xt - DC CGSW, Xt - DC CIGSW, Xt - DC CGVAC, Xt - DC CGVAP, Xt - DC CGVADP, Xt - DC CIGVAC, Xt - DC GVA, Xt - DC IGDVAC, Xt - DC IGDSW, Xt - DC CGDSW, Xt - DC CIGDSW, Xt - DC CGDVAC, Xt - DC CGDVAP, Xt - DC CGDVADP, Xt - DC CIGDVAC, Xt - DC GZVA, Xt *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): New entries for IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA, IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP, CIGDVAC and GZVA. (aarch64_sys_ins_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA, IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP, CIGDVAC and GZVA with DC. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
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Sudakshina Das
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@ -1,3 +1,12 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* testsuite/gas/aarch64/sysreg-4.s: Test IGVAC, IGSW,
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CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
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IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
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CIGDVAC and GZVA with DC.
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* testsuite/gas/aarch64/sysreg-4.d: Likewise.
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* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1,
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@ -35,3 +35,21 @@
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'rgsr_el1'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'gcr_el1'
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[^:]*:[0-9]+: Error: selected processor does not support PSTATE field name 'tco'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'igvac'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'igsw'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgsw'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cigsw'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgvac'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgvap'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgvadp'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cigvac'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'gva'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'igdvac'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'igdsw'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgdsw'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cigdsw'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgdvac'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgdvap'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cgdvadp'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'cigdvac'
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[^:]*:[0-9]+: Error: selected processor does not support system register name 'gzva'
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@ -38,3 +38,21 @@ Disassembly of section \.text:
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.*: d51810a1 msr rgsr_el1, x1
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.*: d51810c3 msr gcr_el1, x3
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.*: d503489f msr tco, #0x8
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.*: d5087661 dc igvac, x1
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.*: d5087682 dc igsw, x2
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.*: d5087a83 dc cgsw, x3
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.*: d5087e84 dc cigsw, x4
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.*: d50b7a65 dc cgvac, x5
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.*: d50b7c66 dc cgvap, x6
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.*: d50b7d67 dc cgvadp, x7
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.*: d50b7e68 dc cigvac, x8
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.*: d50b7469 dc gva, x9
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.*: d50876aa dc igdvac, x10
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.*: d50876cb dc igdsw, x11
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.*: d5087acc dc cgdsw, x12
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.*: d5087ecd dc cigdsw, x13
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.*: d50b7aae dc cgdvac, x14
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.*: d50b7caf dc cgdvap, x15
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.*: d50b7db0 dc cgdvadp, x16
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.*: d50b7eb1 dc cigdvac, x17
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.*: d50b7492 dc gzva, x18
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@ -38,3 +38,26 @@ func:
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# MSR (immediate)
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msr TCO, #8
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# Data cache
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dc igvac, x1
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dc igsw, x2
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dc cgsw, x3
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dc cigsw, x4
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dc cgvac, x5
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dc cgvap, x6
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dc cgvadp, x7
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dc cigvac, x8
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dc gva, x9
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dc igdvac, x10
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dc igdsw, x11
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dc cgdsw, x12
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dc cigdsw, x13
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dc cgdvac, x14
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dc cgdvap, x15
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dc cgdvadp, x16
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dc cigdvac, x17
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dc gzva, x18
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@ -1,3 +1,11 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_sys_regs_dc): New entries for
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IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
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IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
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CIGDVAC and GZVA.
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(aarch64_sys_ins_reg_supported_p): New check for above.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
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@ -4481,15 +4481,33 @@ const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
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const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
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{
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{ "zva", CPENS (3, C7, C4, 1), F_HASXT },
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{ "gva", CPENS (3, C7, C4, 3), F_HASXT | F_ARCHEXT },
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{ "gzva", CPENS (3, C7, C4, 4), F_HASXT | F_ARCHEXT },
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{ "ivac", CPENS (0, C7, C6, 1), F_HASXT },
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{ "igvac", CPENS (0, C7, C6, 3), F_HASXT | F_ARCHEXT },
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{ "igsw", CPENS (0, C7, C6, 4), F_HASXT | F_ARCHEXT },
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{ "isw", CPENS (0, C7, C6, 2), F_HASXT },
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{ "igdvac", CPENS (0, C7, C6, 5), F_HASXT | F_ARCHEXT },
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{ "igdsw", CPENS (0, C7, C6, 6), F_HASXT | F_ARCHEXT },
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{ "cvac", CPENS (3, C7, C10, 1), F_HASXT },
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{ "cgvac", CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT },
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{ "cgdvac", CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT },
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{ "csw", CPENS (0, C7, C10, 2), F_HASXT },
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{ "cgsw", CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT },
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{ "cgdsw", CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT },
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{ "cvau", CPENS (3, C7, C11, 1), F_HASXT },
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{ "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
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{ "cgvap", CPENS (3, C7, C12, 3), F_HASXT | F_ARCHEXT },
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{ "cgdvap", CPENS (3, C7, C12, 5), F_HASXT | F_ARCHEXT },
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{ "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
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{ "cgvadp", CPENS (3, C7, C13, 3), F_HASXT | F_ARCHEXT },
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{ "cgdvadp", CPENS (3, C7, C13, 5), F_HASXT | F_ARCHEXT },
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{ "civac", CPENS (3, C7, C14, 1), F_HASXT },
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{ "cigvac", CPENS (3, C7, C14, 3), F_HASXT | F_ARCHEXT },
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{ "cigdvac", CPENS (3, C7, C14, 5), F_HASXT | F_ARCHEXT },
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{ "cisw", CPENS (0, C7, C14, 2), F_HASXT },
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{ "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
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{ "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
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{ 0, CPENS(0,0,0,0), 0 }
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};
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@ -4632,6 +4650,28 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
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&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
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return FALSE;
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/* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
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if ((reg->value == CPENS (0, C7, C6, 3)
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|| reg->value == CPENS (0, C7, C6, 4)
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|| reg->value == CPENS (0, C7, C10, 4)
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|| reg->value == CPENS (0, C7, C14, 4)
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|| reg->value == CPENS (3, C7, C10, 3)
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|| reg->value == CPENS (3, C7, C12, 3)
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|| reg->value == CPENS (3, C7, C13, 3)
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|| reg->value == CPENS (3, C7, C14, 3)
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|| reg->value == CPENS (3, C7, C4, 3)
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|| reg->value == CPENS (0, C7, C6, 5)
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|| reg->value == CPENS (0, C7, C6, 6)
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|| reg->value == CPENS (0, C7, C10, 6)
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|| reg->value == CPENS (0, C7, C14, 6)
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|| reg->value == CPENS (3, C7, C10, 5)
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|| reg->value == CPENS (3, C7, C12, 5)
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|| reg->value == CPENS (3, C7, C13, 5)
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|| reg->value == CPENS (3, C7, C14, 5)
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|| reg->value == CPENS (3, C7, C4, 4))
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&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
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return FALSE;
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/* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
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if ((reg->value == CPENS (0, C7, C9, 0)
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|| reg->value == CPENS (0, C7, C9, 1))
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